How can I fix the error: can't mix packed and unpacked types?

Question

I am trying to build a 4:1 multiplexer using 2:1 multiplexers that I've built. I am getting a few errors whenever I try typing the command vsim mux4_test.

Array connection type 'reg$[1:0]' is incompatible with 'wire[1:0]' for port (sel): can't mix packed and unpacked types.

Port size (1) does not match connection size (32) for port 'Z'. The port definition is at: NOT.sv(3).

Illegal output or inout port connection for port 'Z'.

And here's my attempt in doing it:

For 2:1 mux:

module mux2 (
    input logic d0,          // Data input 0
    input logic d1,          // Data input 1
    input logic sel,         // Select input
    output logic z           // Output
);


logic w1,w2,w3,w4,w5,w6,w7,w8;
NOT # (.Tpdlh(10), .Tpdhl(8)) g1(.Z(w1) , .A(d0));
OR2 # (.Tpdlh(2), .Tpdhl(6)) g4(.Z(w5), .A(w1), .B(w4));
NOT # (.Tpdlh(10), .Tpdhl(8)) g2(.Z(w2) , .A(d1));
OR2 # (.Tpdlh(2), .Tpdhl(6)) g5(.Z(w6), .A(w2), .B(w3));
NOT # (.Tpdlh(10), .Tpdhl(8)) g3(.Z(w3) , .A(w4));
NOT # (.Tpdlh(10), .Tpdhl(8)) g6(.Z(w7) , .A(w5));
NOT # (.Tpdlh(10), .Tpdhl(8)) g7(.Z(w8) , .A(w6));
OR2 # (.Tpdlh(2), .Tpdhl(6)) g8(.Z(z) , .A(w7), .B(w8));


endmodule

for 4:1 mux:

module mux4 (
    input logic d0,          // Data input 0
    input logic d1,          // Data input 1
    input logic d2,          // Data input 2
    input logic d3,          // Data input 3
    input logic [1:0] sel,   // Select input
    output logic z           // Output
);

logic w1,w2;

mux2 mux2a(
.d0(d0),
.d1(d1),
.sel(sel[0]),
.z(w1)
);




mux2 mux2b(
.d2(d0),
.d3(d1),
.sel(sel[0]),
.z(w2)
);



mux2 mux2c(
.d0(w1),
.d1(w2),
.sel(sel[1]),
.z(z)
);


endmodule

and finally my testbench

module mux4_test;
logic d0,d1,d2,d3,sel[1:0], z;



mux4 m4a(
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.sel(sel),
.z(z)
);




initial begin
d0=1'b0;
d1=1'b0;
d2=1'b0;
d3=1'b0;
sel[0]=1'b0;
sel[1]=1'b0;

#20
d0=1'b1;
d1=1'b0;
d2=1'b0;
d3=1'b0;
sel[0]=1'b0;
sel[1]=1'b0;

end 

endmodule

Answer 1

Port size (1) does not match connection size (32) for port 'Z'. The port definition is at: NOT.sv(3).

Could you please share the definition of NOT.sv? It appears your problem is there (I note you are using your own implementation of those gates rather than the verilog primitives). Looks like you may have a port mismatch between NOT.sv and your 2mux.

Answer 2

1. Array connection type 'reg$[1:0]' is incompatible with 'wire[1:0]' for port (sel): can't mix packed and unpacked types.

Here sel is defined as an unpacked array of 2 single bits:

logic d0,d1,d2,d3,sel[1:0], z;

Here is the definition of the port where sel is defined as packed array (vector) of 2 bits.

input logic [1:0] sel

System verilog does not allow assignments between them. so, the port .sel(sel), causes the issue. To fix, you need to declare both the same way. I suggest to change declaration of the variable to

logic [1:0] sel;

2. Port size (1) does not match connection size (32) for port 'Z'. The port definition is at: NOT.sv(3).

This points to the file NOT.sv, which seems to be a definition of the module NOT. you need to provide this module in your example.

Answer 3

This is a copy of the Answer I posted on electronics.stackexchange.com. I saw the Question there before I realized it was also posted here.

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The 1st compile error I get is related to the sel port.

In module mux4_test, change:

logic d0,d1,d2,d3,sel[1:0], z;

to:

logic d0,d1,d2,d3, z;
logic [1:0] sel;

sel[1:0] (unpacked) is not the same as [1:0] sel (packed).

The 2nd compile error I get is related to the mux2b instance. Change:

mux2 mux2b(
.d2(d0),
.d3(d1),
.sel(sel[0]),
.z(w2)
);

to:

mux2 mux2b(
.d0(d2),
.d1(d3),
.sel(sel[0]),
.z(w2)
);

mux2 does not have d2 and d3 ports.

Your code compiles cleanly for me. I do not see errors related to the Z port; here is the code on edaplayground

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We concluded that the Z error was a bug in the user's simulator. The OP updated to the latest version of ModelSim, and now all errors are gone.