Debug help : enum reg is incompatible with reg port

0
votes

In my module, I have an output port named Cmd which is of 'reg' type. 

module ddesign (clk, rst, addr, data, Cmd);
    input          clk;
    input          rst;
    input [31:0]   addr;
    input [31:0]   data;
   ... 
    output reg [2:0]   Cmd; // this is the signal concerned
   ...
    always @(posedge clk) begin
        if (rst == 0) begin
            Cmd = IDLE; // I wanted to drive enum values 
        end
        else begin
            Cmd = WR;
            ...
         end
     end 

endmodule;

I have also defined the signal Cmd using typedef as shown below in another file. 

typedef enum logic [2:0] {
    IDLE,
    WR,
    RD,
    RDX,
    RDL,
    WRN,
    WRC,
    BROADCAST
} Cmd_t;

The interface is defined like this 

Interface intf (input clk);
   Cmd_t Cmd;
   ...
endinterface

In top file where I instantiated the module,

module top;
     ...
    intf vif(clk); // interface instantiation

     ddesign dut(
        ...
     .Cmd(vif.Cmd), // the module port and interface are connected like this, but here is the incompatibility problem 
        ...
      );
endmodule

so I get the following error:

** Error: (vsim-3906) F:/folder1/project1/DV/top/top.sv(79): Connection type 'file_list_svh_unit.enum reg[2:0] ' is incompatible with 'reg[2:0]' for port (Cmd).

How to resolve this error, provided I can drive enum type values on Cmd signal in my design module?

2
interfacesystem-verilog
You could do with constructing an MCVE. I did so on EDA Playground and found no error. I also tried it on Questa and found no error. – Matthew Taylor

2 Answers

1
votes

Since Cmd is an output port of your design, you are trying to make an assignment from variable that is not an enum to another variable that is an enum. That is not legal without a cast. And SystemVerilog has no way to specify a cast to the target (or lvalue) of an assignment.

So you need to do one of two things:

  • Declare your Cmd port using the Cmd_t type
  • Connect your Cmd port to a compatible variable type in your interface, and use a continuous assignment to cast it to the Cmd_t type.
1
votes

Normally it is not legal to assign an enum to a valued not of the same type without casting. However, there is a workaround by specifying the bit range on the enum. It works a the simulators I tried. I'm not sure if this workaround is an intended or unintended feature of the simulator or the LRM itself. 

ddesign dut(
  .Cmd(vif.Cmd[2:0]), 
  .* );