Is it possible to use a type defined with "typedef enum" in a module's port declaration?

Question

I'm trying to understand how typedef and enum work in SystemVerilog and, in particular, if it's possible to use a "custom" data type in a module's port declaration.

So far, I've been able to create a custom data type in a package, here it is:

typedef enum logic[2:0] {
        add_conf = 3'b000,
        sub_conf = 3'b001,
        and_conf = 3'b010,
        or_conf = 3'b011,
        xor_conf = 3'b100,
        sll_conf = 3'b101,
        srl_conf = 3'b110,
        sra_conf = 3'b111
} iexu_conf

Now, I'd like to define an input port of type iexu_conf in a module, like this:

module iexu_decoder
(
    input iexu_conf conf,
    output logic add_ctrl,
    output logic[1:0] logic_ctrl,
    output logic[1:0] shifter_ctrl,
    output logic[1:0] outmux_ctrl
);

Is this possible? If so, is the syntax correct? I'm currently getting problems with Modelsim

** Error: (vlog-13069) iexu_decoder.sv(5): near "conf": syntax error, unexpected IDENTIFIER, expecting ')'.

but I can't tell if it's because of some stupid mistake or if it's due to a more serious conceptual error.

yes it is possible. which compiler did you use? did you compile in system verilog mode? you are missing semicolon after typedef decl. are there other errors? — Serge
I did not copy-pasted the semicolon but it's there, I'm using ModelSim - Intel FPGA Edition vlog 10.5b Compiler. Matter of fact, I did not import correctly the package, so no wonder the compiler didn't recognize the type. — Sandro Sartoni

dave_59 dave_59 · Accepted Answer · 2019-01-13T06:51:34

If you put the typedef in a package, you need to explicitly reference the package or import it to be visible in all module declarations that use it.

package pkg;
  typedef enum logic[2:0] {
        ...
  } iexu_conf;
endpackage

Explicit reference:

module iexu_decoder
(
    input pkg::iexu_conf conf,
    output logic add_ctrl,
    output logic[1:0] logic_ctrl,
    output logic[1:0] shifter_ctrl,
    output logic[1:0] outmux_ctrl
);

Module header import:

module import pkg::*; iexu_decoder
(
    input iexu_conf conf,
    output logic add_ctrl,
    output logic[1:0] logic_ctrl,
    output logic[1:0] shifter_ctrl,
    output logic[1:0] outmux_ctrl
);

Is it possible to use a type defined with "typedef enum" in a module's port declaration?

1 Answers