a few issues about 'tri' data type in SystemVerilog

Question

I just started to use the 'tri' datatype these days. And I've applied this datatype in two different modules. It serves the first module nicely in terms of logic and structural simulation (before synthesis), where basically I have a bunch of logic wires assigned to the same tri, like this:

logic wire1;
logic wire2;
logic wire3;
tri tri1;

assign tri1 = wire1;
assign tri1 = wire2;
assign tri1 = wire3;

In IEEE Standard for SystemVerilog, it says

A wire net can be used for nets that are driven by a single gate or continuous assignment. The tri net type can be used where multiple drivers drive a net. Logical conflicts from multiple sources of the same strength on a wire or a tri net result in x (unknown) values.

So I assume it works like the codes above. However, when I applied the same logic to my second module,

integer var_a, var_b, var_c, var_cnt;
logic arrWire1[1:0][3:0];
logic arrWire2[1:0][1:0];
logic arrWire3[1:0];
tri triArrWire[7:0];

always_comb begin
  var_cnt = 7;
  for (var_a=1; var_a<=0; var_a--) begin
    for (var_b=1; var_b<=0; var_b--) begin
      for (var_c=(1+var_b*2); var_c<=var_b*2; var_c--) begin
        triArrWire[var_cnt] = arrWire1[var_a][var_c];
        triArrWire[var_cnt] = arrWire2[var_a][var_b];
        triArrWire[var_cnt] = arrWire3[var_a];
        var_cnt --;
      end
    end
  end
end

ModelSim complaints about it:

(vlog-2110) Illegal reference to net "triArrWire".

Basically what the 2nd module does is to simply mimic the 1st module, but in a always_comb block. But why it doesn't pass the ModelSim compile check? Am I missing something here?

On another note, is it usual to connect different wires to one single wire? The reason I am doing it is because most of the wires will be on high impedance 'z', and only one of them will have 0 or 1 and drive the tri net. This makes me want to merge them into one tri net so that it's easier to make it as output of the module.

Any thoughts are welcome. I very much appreciate your help here.

Taihai

dave_59 dave_59 · Accepted Answer · 2015-06-26T23:57:29

You are not allowed to make procedural assignments to wires.. To make a connection, you need to use a continuous assignment as you did in the 1st module.. To do that, you need a generate-for loop.. Something like:

for (genvar var_a=1; var_a<=0; var_a--) begin
  for (genvar var_b=1; var_b<=0; var_b--) begin
     for (genvar var_c=(1+var_b*2); var_c<=var_b*2; var_c--) begin
        parameter var_cnt = (some expression of var_a and var_b); 
        assign triArrWire[var_cnt] = arrWire1[var_a][var_c];
        assign triArrWire[var_cnt] = arrWire2[var_a][var_b];
        assing triArrWire[var_cnt] = arrWire3[var_a];
     end
  end
end

I'll leave it to you to figure out the expression, it should not be too difficult...

a few issues about 'tri' data type in SystemVerilog

1 Answers