How to properly implement a time delay in a SystemVerilog module that uses the always_comb construct?

Question

I'm hoping someone can explain how to properly implement gate delays for a combinational function in SystemVerilog. Why is it ok to implement time delays using #(1) in an always block but not an always_comb? The code below gives this error ...

Statements in an always_comb shall not include those that block, have blocking timing or event controls, >or forkjoin statements.

module compare( input logic [3:0] a,
                input logic [3:0] b,
                output logic eq );
  always_comb
    if (a != b) 
      #(1) eq = 1'b0;
    else
      #(1) eq = 1'b1;
endmodule

Changing always_comb to always gets rid of the error and implements the delays. But how would you simulate a propagation delay and retain the always_comb? I tried to implement a specify block in this module by adding ...

specify
 (a => eq) = (1);
 (b => eq) = (1);
endspecify

... and this will implement the time delay ... but only if I change the type of a and b from logic to wire. Is there a way to implement the delay, retain always_comb and keep a and b as logic? What makes always_comb so different? I'm only just beginning to learn SystemVerilog, so any insight would be greatly appreciated.

dave_59 dave_59 · Accepted Answer · 2020-03-25T03:55:11

You are running into tool issues. Ports a and b should implicitly be wires. You can try another tool or make it explicit with:

module compare( input wire logic [3:0] a,
                input wire logic [3:0] b,
                output logic eq );
  specify
    (a *> eq) = (1);
    (b *> eq) = (1);
endspecify

  always_comb
    if (a != b) 
       eq = 1'b0;
    else
       eq = 1'b1;
endmodule

Also, the since you have a many-to-one paths, you need to change => to *>

How to properly implement a time delay in a SystemVerilog module that uses the always_comb construct?

1 Answers