How to understand the blocking and non blocking statements in verilog?

Question

I understood the basic difference between blocking and non-blocking statements in Verilog. But still it is not possible for me to understand what's happening & when and where to use blocking and non-blocking statements. For example, consider simple d ff code:

module dff (clk, reset,d, q, qb);
input      clk;
input      reset;
input      d;
output     q;
output     qb;

reg        q;

assign qb = ~q;

always @(posedge clk or posedge reset)
begin
  if (reset) begin
    // Asynchronous reset when reset goes high
    q <= 1'b0;
  end else begin
    // Assign D to Q on positive clock edge
    q <= d;
  end
end
endmodule

But if I write the very same logic using two-segment coding technique:

module dff(input wire d,
           clk,
           reset,
           en,
           output wire q);

reg q;
reg r_reg, r_next;

always @(posedge clk, posedge reset)
if(reset) 
  r_reg<=1'b0;
else
  r_reg<=r_next;

always @*
  if(en)
    r_reg=d;
  else
    r_reg=r_next;

assign q<=r_reg;
endmodule

Now, in this code, I just didn't understand why are using <= in the first always block and why they are using = in 2nd always block. I also know that in combinational logic circuit = is advised to use & in sequential <= this is advised to use. But still, I couldn't be able to find out the answer to the usage of blocking and non-blocking statements. Can you please help me!?

Your second example does not represent the same logic-- it has an en input that the first example does not. It is also not syntactically correct. Please fix that and it might become clearer to you, or if not, someone would be able to answer the question. — dave_59

Serge Serge · Accepted Answer · 2020-02-01T18:57:01

Blocking/non-blocking assignments is a simulation artifact only. Contrary to the believe, verilog does not describe hardware. Verilog describes desired behavior of the hardware trying to fit it into an event-driven simulation scheme.

Here is a simple example of a shift register which employs 2 flops:

    always @(posedge clk)
        out1 = in;
    always @(posedge clk)
        out2 = out1;

Now, what would the output of the out2 be? Since we are dealing with simulation, then it depends on the order in which these 2 statements are executed. Either it will be the old value of out1, or the new one (actually the value of in);.

In hardware there is no such mess. It will flop the value which existed at the posedge time, the old value of out1 (well, unless there are unusual delays in clocks).

In order to match this behavior, the non-blocking assignment was introduced. Verilog simulation is done in simulation ticks. Every tick is as long as there are events which could cause re-evaluation of other blocks. The non-blocking assignments are scheduled to be executed at the end of such a tick with current rhs values ( in reality there are several scheduling zones). So, consider the following:

    always @(posedge clk)
        out1 <= in;
    always @(posedge clk)
        out2 <= out1;

In the above example the all assignments will happen at the end of the tick. 'out2` will be assigned a value which existed at the time of the <=, so, it will be the old value of out1. Now, it does not matter in which order they are executed.

So, the top-level recommendation is to use blocking assignments (=) for combinational logic and use non-blocking assignments (<=) for all outputs of state devices, flops and latches. Note that some temporary variables inside state devices, which are only used there internally should also be assigned with blocking. Also, never use non-blocking assignments in clock trees.

How to understand the blocking and non blocking statements in verilog?

1 Answers