I am writing a SystemVerilog Testbench for a module that models a schematic, but don't know why transcript window saying no connection to port Y?

Question

The Following schematic is what I have modeled my module from. This is a SystemVerilog HW assignment in which we must use contiuous assignment(s). The signature model was given to us. Note there is no delays in the circuit. The problem I am having is that I don't really know what I am doing, for I am new to SystemVerilog and this is first time I have to write my own Testbench. schematic to model

Here is the module code:

module hw2_prob1 (
  input logic A, B, C, D,
  output logic Y
);  

  assign Y = (~(A|D)) & (B & C & ~D);


endmodule

This is what I have for my testbench code so far:

timeunit 1ns/1ns;

module tb_hw2_prob1();
 reg A, B, C, D;
 wire Y;



hw2_prob1 DUT(A, B, C, D, Y);

initial begin
#5 {A,B,C,D} = 4'b0000;
#5 {A,B,C,D} = 4'b0001;
#5 {A,B,C,D} = 4'b0010;
#5 {A,B,C,D} = 4'b0011;

#5 {A,B,C,D} = 4'b0100;
#5 {A,B,C,D} = 4'b0101;
#5 {A,B,C,D} = 4'b0110;
#5 {A,B,C,D} = 4'b0111;

#5 {A,B,C,D} = 4'b1000;
#5 {A,B,C,D} = 4'b1001;
#5 {A,B,C,D} = 4'b1010;
#5 {A,B,C,D} = 4'b1011;

#5 {A,B,C,D} = 4'b1100;
#5 {A,B,C,D} = 4'b1101;
#5 {A,B,C,D} = 4'b1110;
#5 {A,B,C,D} = 4'b1111;
end

initial begin #500 $finish; 
end

initial begin $monitor ($time,"%h %b", {A,B,C,D},Y);
end

endmodule

The assignment asks for 'The testbench for this circuit should set up a $monitor() statement in one initial block and generate all of the possible input combinations with a #5 ns delay between changing the inputs.' We use QuestaSim or ModelSim for the simulations and here is the transcript and wave windows. Snip of tb project window Snip of wave window tb

Do I have to add a clock? Why does it say missing connection for port Y? Does my wave window seem correct?

Greg Greg · Accepted Answer · 2020-05-05T00:17:11

hw2_prob1 DUT(Y, A, B, D); is missing C and has the wrong port order.

Pick one:

hw2_prob1 DUT(A, B, C, D, Y); // connect by port order
hw2_prob1 DUT(.Y(Y), .A(A), .(B), .C(C), .D(D) ); // explicit connect by port name
hw2_prob1 DUT( .Y, .A, .B, .C, .D ); // implicit connect by port name
hw2_prob1 DUT( .* ); // auto connect by port name

I am writing a SystemVerilog Testbench for a module that models a schematic, but don't know why transcript window saying no connection to port Y?

1 Answers