Multi-dimensional alias in VHDL

Question

I would like to ask if it is possible to use alias with multi dimensional arrays in VHDL and how to solve (1).

I have the following array defined at the beginning of the architecture>

subtype WORD8 is STD_LOGIC_VECTOR (7 downto 0);  
type IMEM is array (0 to 576) of WORD8;
signal MEM: IMEM;

Through the program I use processes and I alias a part of the memory like so>

alias Version: STD_LOGIC_VECTOR (3 downto 0) is MEM(0)(3 downto 0);
alias IHL: STD_LOGIC_VECTOR (3 downto 0) is MEM(0)(7 downto 4);

This following line is alias too, both of the lines work

alias TOS: STD_LOGIC_VECTOR (7 downto 0) is MEM(1);
alias TOS: STD_LOGIC_VECTOR (7 downto 0) is MEM(1)(7 downto 0);

Now I have a data which is larger than WORD8, of length 2xWORD8. I tried the following code but, without success. It causes>

Error: indexed name is not a 'std_logic_vector'

--(1) How to solve this?
alias TL: STD_LOGIC_VECTOR (15 downto 0) is MEM(3 downto 2);

This line also gives the same error>

alias TL: STD_LOGIC_VECTOR (15 downto 0) is MEM(3 downto 2)(7 downto 0);

I was experimenting a workaround, but also with no success>

alias TL2: STD_LOGIC_VECTOR (7 downto 0) is MEM(2);
alias TL3: STD_LOGIC_VECTOR (7 downto 0) is MEM(3);
alias TL4: STD_LOGIC_VECTOR (15 downto 0) is TL3&TL2;

(1) The type of alias TL is std_logic_vector while the type of MEM is IMEM. IEEE Std 1076-2008 6.6.2 Object aliases "The base type of the name specified in an alias declaration shall be the same as the base type of the type mark in the subtype indication (if the subtype indication is present)." For TL4 6.6.1 "The alias designator in an alias declaration denotes the named entity specified by the name and, if present, the signature in the alias declaration. ", where the expression TL3&TL2 is not a named entity. — user1155120
Also type IMEM is not a multidimensional array type, it has only one index (5.3.2 Array types, 5.3.2.1 General). It's element type happens to also be a single dimensional array type. With that caveat the answer to I would like to ask if it is possible to use alias with multi dimensional arrays in VHDL is yes, and your erroneous alias (1) is not related to the question. A multi-dimensional array cannot be sliced ("The prefix of a slice shall be appropriate for a one-dimensional array object." 8.5 Slice names). — user1155120
Object aliases for multi-dimensional array types are supported in IEEE Std 1076-2008 6.6.2 Object aliases. It's unclear how widely supported this 'new' feature is among the various tool implementations. — user1155120

Tricky Tricky · Accepted Answer · 2020-02-09T14:26:55

This is all because of strong typing in VHDL and because of the rules of aliases. Aliases must be directly to an object of the same type. It cannot also be to a new object that is not from a declaration, such as a function return. All of your errors because of these limitations.

std_logic_vector(7 downto 0) is a 1d array of std_logic. MEM(3 downto 2)(7 downto 0) is a 1d array of std_logic_vectors. So not the same type

TL3 & TL2 is not a declared object, it is a function return value.

Your only solution would be to use a signal (or variable) because you are creating a new subtype.

signal TL4: STD_LOGIC_VECTOR (15 downto 0);

TL4 <= TL2 & TL3;

Multi-dimensional alias in VHDL

1 Answers