Slice from a matrix to a vector in VHDL2008

0
votes

I have a two dimensional matrix of type 'std_logic_vector' of which I need to slice one column or line to extract an (one dimensional) array of type 'std_logic_vector'. I have this problem using the VHDL2008 standard. I am aware that nested arrays would solve my issue, though I am curious if a solution using matrices exists.

Trying to give to the matrix only one index does not give me an array, but results in an error that the type can not be resolved.

Definition of the matrix: 

library IEEE;
    use IEEE.STD_LOGIC_1164.all;

package package1 is
    type MATRIX_TYPE is array (natural range <>, natural range <>) of std_logic_vector;

    type VECTOR_TYPE is array (natural range <>) of std_logic_vector;
end package1;

Entity of subcomponent:

library IEEE;
   use IEEE.STD_LOGIC_1164.all;
library WORK;
   use WORK.PACKAGE1.ALL;

entity subcomponent is
   port (
       input_vector : in  VECTOR_TYPE;
   );
end subcomponent;

architecture arch of subcomponent is
begin
end architecture;

Top component where problem occurs:

library IEEE;
   use IEEE.STD_LOGIC_1164.all;
library WORK;
   use WORK.PACKAGE1.ALL;

entity component1 is
end entity;

architecture arch of component1 is

   constant subcomponents : integer := 10;
   signal matrix : MATRIX_TYPE (0 to subcomponents - 1, 0 to 15) (31 downto 0);

begin

   SUBCOMPONENT_ARRAY : for i in 0 to subcomponents - 1 generate
       subcomponent_i : entity work.subcomponent(arch)
       port map (
           input_vector => matrix(i) --matrix(i) does not work!
       );
   end generate;

end architecture;
2
matrixmultidimensional-arrayvhdlslice
--matrix(i) does not work! isn't a particularly descriptive error statement and lacking a minimal reproducible example can't be reproduced. The apparent error is the dimensionality of the indexed name matrix(i) not matching the dimensionality of MATRIX type (0 to subcomponents - 1, 0 to 15). Note the lack of subtype indication for the incomplete type VECTOR_TYPE and it's element subtype in the port declaration for input_vector in entity subcomponent. - user1155120
@user1155120 Thank you for completing my example. The missing parts were trivial, but admittedly still missing. With your permission I would copy the missing parts to my question to make the example working. - alexgk
Neither answer shows how to apply a solution to your as yet unclear problem. Clear up what you mean by "...slice one column or line". Is that then enough for a future reader using your question and accepted answer found as a search resource to understand your problem and then apply your accepted solution to their own problem? The idea is questions and their accepted answers are a search resource. As it stands now how to apply the accepted answer to an unclear question isn't found. - user1155120

2 Answers

0
votes

I think something like this could work:

SUBCOMPONENT_ARRAY : for i in 0 to subcomponents - 1 generate
   block_label : block
      signal temp_vector : VECTOR_TYPE(0 to 15) (31 downto 0);
   begin
      SUBVECTOR_ARRAY : for j in 0 to 15 generate
         temp_vector(j) <=  matrix(i,j);
      end generate;

      subcomponent_i : entity work.subcomponent(arch)
         port map (
            input_vector => temp_vector
         );
   end block block_label;
end generate;

You extract the matrix elements one by one and assign them to a temporal vector, then pass the temporal vector to the subcomponent.

0
votes

Unfortunately, you cannot slice a 2+ D array in VHDL. So you either have to stick with nested 1D arrays for easy slicing, or create a slicing function to do what you want.

function slice_row(m : MATRIX_TYPE; row : integer) return VECTOR_TYPE is
  variable r : VECTOR_TYPE(m'range(2))(m'element'range);
begin
  for i in r'range loop
    r(i) := m(row, i);
  end loop;

  return r;
end function;