Understanding types and subtypes vs. signals

Question

I currently have a bug between two version of a VHDL simulator

my code (simple version to trigger the error)

library ieee;
use ieee.std_logic_1164.all;

entity test is
end;

architecture test of test is
    constant mpc_ibif_data_width          : integer := 16;
    subtype  t_mpc_ibif_data              is std_logic_vector (mpc_ibif_data_width - 1 downto 0);

    type t_device_2_mpc_ibif is
      record
        rd_data     : t_mpc_ibif_data;  --
        rd_data_en  : std_logic;        -- '1': rd_data must be driven to the CPU
        berr_n      : std_logic;        --
    end record;

    type  t_device_2_mpc_ibif_array    is array (natural range <>) of t_device_2_mpc_ibif;
    signal flash_cnt_2_mpc_o : t_device_2_mpc_ibif;
begin
    process 
    begin
        wait for 10 ns;
        assert flash_cnt_2_mpc_o.rd_data = t_device_2_mpc_ibif.rd_data'(others => '0') report"flash_cnt_2_mpc_o.rd_data should have been deasserted" severity error;
        wait;
    end process;
end;

In the first version the following is legal

assert flash_cnt_2_mpc_o.rd_data = t_device_2_mpc_ibif.rd_data'(others => '0') report"flash_cnt_2_mpc_o.rd_data should have been deasserted" severity error;

However in a new version, I get a "Type Error" on the same line. Specifically on

t_device_2_mpc_ibif.rd_data'(others => '0')

I created this as a bug at vendor who tells me to use below code:

assert flash_cnt_2_mpc_o.rd_data = t_mpc_ibif_data'(others => '0') report"flash_cnt_2_mpc_o.rd_data should have been deasserted" severity error;

based on these arguments

In this context the type is expected not its selection.

Here is what I do not understand and want an answer to:

To my understanding there are types and subtypes. subtypes inherit from types

So when you create a signal

signal NameOfSignal : std_logic_vector(1 downto 0)

This signal now inherit all from std_logic_vector plus its contrained IE it's a "subtype" of the type std_logic_vector.

And regardless of the signal is in a record or not should not change this fact.

I asked this and got the following answer:

t_device_2_mpc_ibif.rd_data It is not type_name neither subtype_name but selected name (element name of record).

But in my world this shouldn't matter since the signal(element) inherit all of the types methods.

Please correct me because I clearly misunderstand something

EDIT: I used VHDL2008

Regards Anders

scary_jeff scary_jeff · Accepted Answer · 2015-10-08T13:25:42

Your problem code:

t_device_2_mpc_ibif.rd_data'(others => '0')

In this line, you are trying to qualify (others => '0') as type t_device_2_mpc_ibif.rd_data. The problem, and what tech support have said, is that rd_data isn't a type, so you can't qualify anything as it. There is no syntax for "qualify this as the same type as the supplied signal".

Examples:

signal foo : std_logic_vector (1 downto 0);
subtype MyType is std_logic_vector (1 downto 0);
signal bar : MyType;

...

-- Simple assignment, OK
foo <= "00";

-- Qualify the literal "00" as a type std_logic_vector, OK
foo <= std_logic_vector'("00");

-- Simple assignment; subtypes have automatic conversion to/from the parent type, OK
bar <= "00";

-- Qualify the literal "00" as type 'foo', not OK, since 'foo' isn't a type.
bar <= foo'("00");

-- Qualify the literal "00" as type 'MyType', OK.
bar <= MyType'("00");

-- Qualify the literal "00" as type 'bar', not OK, since 'bar' is not a type.
bar <= bar'("00");

This issue has nothing to do with sub types or records. If your original code worked in an older tool version, this was a bug.

Understanding types and subtypes vs. signals

Here is what I do not understand and want an answer to:

2 Answers