How could I generate signal output as a slow clock domain that is a multiple of a fast clock domain?

0
votes

I have an FPGA which I have 40-60 MHz clock domain I am working with. My output will be a slow multiple of that clock domain.

So if I have 40 MHz oscillator, the output interface would be 5 MHz.

I was planning on using a clock divide by 2 and sending the signal to the input, but I don't like this design because I read about how I would need to send the signals through a clock buffer which I may not have enough resources and others have stated it could create hold violations. (https://www.thecodingforums.com/threads/pulse-stretching.377607/)

My second idea is to use a counter that counts the amount of time required to hold the Q output of a DFF and apply back pressure to source logic.

I currently do not have code. I am still thinking of it conceptually.

The initial plan was use several clock divide by 2 block in series to get the output desired.

For signals that seem like a 5 MHz clock domain but were generated with a 40 MHz clocked system, what is the terminology for this type of clock domain crossing?

Are there any other options?

Thank You

1
vhdlclockdigital
It's not clear what the output interface is. At least provide the entity/module signals you're using. – Oron Port
The output would be Clock Data Enable. But I would like to transform any 4x clock domain signal to an x clock domain signal. So a 40 ns pulse high should be a 160 ns pulse. – Cit5
40 Mhz divided down to 5 MHz requires a divisor of 8, not 4. But this doesn't really matter for your question. – the busybee
Do you need the slow clock outside of the FPGA or inside for the rest of your logic? FPGAs used to have multiple clock buffers giving multiple clock domains. You should be able to feed a second clock buffer with the output of the divider. Which FPGA do you plan to use? – the busybee
If the 5Mhz clock is used only externally, then you are often ok just driving it directly from an output pin from logic. – Tricky

1 Answers

0
votes

This is a synchronous CDC, and the counter approach belongs to a class of FSM based clock dividers.