Determining clock frequency on FPGA Spartan-6

Question

I'm working to learn how to program an FPGA in VHDL and want to know how I can determine the correct frequency of my clock input.

I have used the Sp605 Hardware User Guide, pin K21 which in the Clock Source Connections table (pg 27 if you're interested!) is described as being "200 MHz OSC SYSCLK_P".

I then used the following process in order to try and create a 1 Hz clock from the 200 MHz clock

prescaler : process(CLK)
begin
    if rising_edge(CLK) then
        if (counter < 1000000) then --possibly change to number in binary
            counter <= counter + 1;
        else
            CLK_1Hz <= not CLK_1Hz;
            counter <= (others => '0');
        end if;
    end if;
end process;

However, if I set the counter upper limit to be 100,000,000 - which it should be, the clock is far far slower than 1 Hz - in fact using the current value of 1,000,000 counts gives a close approximation of a 1 Hz pulse - but why is this?

Your code is counting for 100 Hz: the counter -> divide by 1,000,000 and the embedded T flipflop -> divide by 2. — Paebbels

FRob FRob · Accepted Answer · 2015-11-02T22:59:19

I think you mean to say that you are currently using K21 OSC SYSCLK_P as a single-ended clock input and directly connected it to CLK. Please include a snippet of your UCF file for reference in future questions.

This won't work, because the individual differential clock lines' peak-to-peak voltage will not reliably register as logical 0 or 1 respectively with a non-differential (LVCMOS25?) I/O standard.

You'll have to

include both _P and _N ports on your entity,
instantiate an LVDS buffer in your design, and
connect _P and _N ports to the buffer in order to get CLK from the buffer's output O

Don't forget to change the I/O standard in your UCF file.

Determining clock frequency on FPGA Spartan-6

1 Answers