Does simulation always show signal/output assignment on clock edge?

Question

So I understand that if we assign a signal or output in a clocked process that the assignment happens on the falling edge or in other words when a process suspends, but why is it that during simulation signals or outputs get assigned during the rising edge of the clock? As an example I have the following code:

 if(rising_edge(clk)) then
     if(one_second_counter = "10111110101111000001111111")
         one_second_counter <= (others=> '0');
     else
      one_second_counter <= one_second_counter + 1; --
 end if;

I have attached simulation waveform:

Unknown Unknown · Accepted Answer · 2017-02-28T02:54:19

So I understand that if we assign a signal or output in a clocked process that the assignment happens on the falling edge or in other words when a process suspends…

This is incorrect. The assignment happens when the sensitivity condition for the process is met. In your example, this is rising_edge(clk) -- the rising edge of the clock.

Does simulation always show signal/output assignment on clock edge?

1 Answers