VHDL Saving input value into another signal

Question

I have a question for my VHDL code. My entire code has to do the following:

input = Minutes + hours + clk
output = AFTER 1 minute: minuten = minuten + 1 (and if needed hours += 1)

So I built a counter, which counts (well for simulation easyness to 1/10th of a second instead of a minute) clock periods untill one minute is over. Then it raises the minute by 1, and send that to the output. I got one problem however: due to setup violation I can't simulate the synthesis well. I thought this violation was in the line: min_save = minutes. I think that it's impossible to save the input minutes immediately, so I thought: let's build another counter, which counts 1 clock period, and then saves it.

So my 2 questions:

Does this indeed solve the setup violation?
If so: why does the signal setup have no value. It has a value of undefined. What do i do wrong?
If not: why not, and how can I solve this then?

CODE:

architecture behaviour of internclk_u is
begin
process (minuten)
begin                -- switching input minutes to binary. 
  minintern(6) <= minuten(0);
  minintern(5) <= minuten(1);
  minintern(4) <= minuten(2);
  minintern(3) <= minuten(3);
  minintern(2) <= minuten(4);
  minintern(1) <= minuten(5);
  minintern(0) <= minuten(6);
end process;

process (uren)
begin                        -- switching input hours to binary
  uurintern(5) <= uren(0);
  uurintern(4) <= uren(1);
  uurintern(3) <= uren(2);
  uurintern(2) <= uren(3);
  uurintern(1) <= uren(4);
  uurintern(0) <= uren(5);
end process;
process (clk)
begin   
    setup <= '0';
    if(clk'event and clk = '1') then
            if(setup < '1') then
                    setup <= '1';
            else
                    setup <= setup;
                    if(min_save = minutes) then
                    count <= new_count;
                    else
                    min_save <= minutes;
                    count <= (others => '0');       
                    end if;
            end if;
    end if;
end process;

process (count, minintern)
begin                   -- count one minute (now its 0.1 second)
if(count < F/10 ) then
    new_count <= count + 1;
    intern_out <= minintern;
    uurintern_out <= uurintern;
else
    case minintern is               -- Calculate new value for output
    when "0001001" => intern_out    <= "0010000";
                      uurintern_out <= uurintern;
    when "0011001" => intern_out    <= "0100000";
                      uurintern_out <= uurintern;
    when "0101001" => intern_out    <= "0110000";
                      uurintern_out <= uurintern;
    when "0111001" => intern_out    <= "1000000";
                      uurintern_out <= uurintern;
    when "1001001" => intern_out    <= "1010000";
                      uurintern_out <= uurintern;
    when "1011001" => intern_out    <= "0000000";
                      case uurintern is
                        when "001001" => uurintern_out <= "010000";
                        when "011001" => uurintern_out <= "100000";
                        when others   => uurintern_out <= uurintern + 1;
                        end case;
    when others       => intern_out    <= minintern + 1;
                      uurintern_out <= uurintern;
    end case;
    new_count <= count;
    setup <= '0';
end if;
end process;

process (intern_out)   -- Reversing signals for next blocks in system
begin
  interne_tijd_m(6) <= intern_out(0);
  interne_tijd_m(5) <= intern_out(1);
  interne_tijd_m(4) <= intern_out(2);
  interne_tijd_m(3) <= intern_out(3);
  interne_tijd_m(2) <= intern_out(4);
  interne_tijd_m(1) <= intern_out(5);
  interne_tijd_m(0) <= intern_out(6);
end process;

process (uurintern_out)
begin                     -- Reversing signals for next blocks in system
  interne_tijd_u(5) <= uurintern_out(0);
  interne_tijd_u(4) <= uurintern_out(1);
  interne_tijd_u(3) <= uurintern_out(2);
  interne_tijd_u(2) <= uurintern_out(3);
  interne_tijd_u(1) <= uurintern_out(4);
  interne_tijd_u(0) <= uurintern_out(5);
end process;
end behaviour;

Remarks:

ignore the 2 case statements; this is because the inputsignals are not binary coded; they are reversed. Besides that: it doesnt count 1,2,4,8,16 etc; it counts: 1,2,4,8,10,20 etc.

EDIT

I put in the whole architecture now. The error message I received was something like: "Setup time violations occured(?)". So I believe I cant save the input minutes immediately when I receive minutes. Thats why I tried to program in the setup signal. Hope you guys can help. This error gave me a headache and lots of frustration already:(

EDIT 2

Forget about the whole "setup" signal. A student-assistent pointed out to me that the saving of the input doesnt make any sense. So my updated question is: How can I properly save the input signal/value into another signal?

Can you copy+paste the actual timing error that you are seeing in your timing report? — Russell
This line setup <= '0'; makes the process it's in not a standard clocked process, so your simulation will never match synthesis. — wjl
The exact error message would be helpful, as it also ought to contain the names of the nets with the violations. Are these error messages from the simulator or the synthesis tool? tell us exactly the tool and version — Martin Thompson
I currently can't reproduce the error message, since I can't the program for synthesise not at home. I used a program called "Go with the flow" for making the VHDL scripts. I used "ModelSim" for the simulations for both the VHDL scripts and the synthesised code from Go With The Flow. All the lines with "setup" weren't there when I synthesised the VHDL scripts. The whole "setup" signal wasn't there. — Earless

Scola Scola · Accepted Answer · 2013-12-04T16:51:25

Your code is really a mess, and it's very difficult to debug... :-( I think that the problem is due to the fact that you have a multiple definition of the signal setup. Moreover the first time is defined inside a clocked process (even if the setup <= '0' is outside the if statement). The second time is defined inside another process that is not clocked. I think that the synthesis tool doesn't know how to proceed exactly. In the simulation of the RTL code you should normally see some glitches on the setup signal. I also think that the type of setup is set_logic. Try to change it to std_ulogic. The simulation tool will not compile your code since this type is unresolved. Fix the code and then go back to std_logic. Another thing: you wrote if setup < '1' then: this sounds very strange to me (I didn't know that it was accepted). I prefer to write if setup /= '1' then: it is much more easier to read this kind of code...

VHDL Saving input value into another signal

1 Answers