Break or return from always_ff / always_comb

Question

Is it possible to break from always block in Verilog? I have a large block and it will be more readable with breaks, comparing to multiple nested if/else statements.

So I want something like this:

always_ff @(posedge clk) begin
   ...

   if (x) begin
      ... 
      break;
   end

   ...
end

I've found one solution, but it looks like a hack:

always_ff @(posedge clk) begin
repeat(1) begin

   ...

   if (x) begin
      ... 
      break;
   end

   ...
end
end

Answer 1

You can put your code in a function, and use return instead of break

always_ff @(posedge clk) func1;
function void func1;
   if (x) begin
      ... 
      return;
   end

   ...
endfunction

This is synthesizable and takes almost the same amount of keystrokes.

Answer 2

There is no way to do what you want in a synthesizable code. Also having a large ff block usually means bad verilog programming style in any case. You should try to split the big always block into a number of separate smaller alway_... blocks.

The purpose of synthesizable verilog code is to describe behavior of the hardware which you want to implement. In hardware there are no 'breaks'. Every always_ff block describes a flop, probably with some additional logic. But in general it should look like this:

 always_ff @(posedge clk)
      out <= in;

if you add more stuff to the block, you have to have a very good reason to do so. Large ff blocks will make people frown.

So, again, you should split your always_ff into a set of flops and combination logic: always_ff and always_comb. This way you will make it more readable and avoid multiple issues which might result from large ff blocks.