(VHDL) Write a double flip flop to resolve meta stability associated with asynchronous input data

Question

Background

I'm new to VHDL and trying to understand how to code a double flip flop to handle metastability associated with a user pressing a button on my fpga board (Cyclone V). I understand the logic behind using a double flip flop to stabilize the data, but unsure how to implement in VHDL.(Sources: related StackOverflow question, eetimes article)

Question

I'm not sure how to code the double flip flop (see my attempt below). Can someone please provide sample code that shows a working double flip flop?

Example code of my attempt at a double flip flop

--input is std_logic;
input <= key(0) -- user pressed key =1, key can be pressed and held

process(input)
   signal inputFF : std_logic;
begin
   if rising_edge(clock) then
      inputFF<= input;
      if input = '1' and inputFF = '1' then
          -- enter if-statement: user pressed the key and the data was 
          -- synchronized by going through a double flip flop?
      end if;
   end if;
end process;

My thoughts: I'm not sure if the if-statement is acting as a double flip flop or not. I pass the input to the inputFF on the rising_edge and then check if the input and inputFF are equal to 1.

Your code only has a single FF. To have a double register, you'll need two signals assigned, one from input, and another from the first FF. Remember the first FF has a chance to be meta-stable, so you're only safe reading the 2nd FF in the chain. — Tricky
@Tricky Thanks for the reply. This is exactly where I'm lost. You're saying I need to make a second signal (inputFF2). Assign inputFF2 <= inputFF. Then in the if-statement I would only check if inputFF2 = '1'? — bsheps

Matthew Taylor Matthew Taylor · Accepted Answer · 2018-10-15T14:57:41

Here's one flip-flip:

process (clock)
begin
   if rising_edge(clock) then
      inputFF <= input;
   end if;
end process;

Here's another:

process (clock)
begin
   if rising_edge(clock) then
      inputFF2 <= inputFF;
   end if;
end process;

Most people would save some lines of code by combining them like this:

process (clock)
begin
   if rising_edge(clock) then
      inputFF  <= input;
      inputFF2 <= inputFF;
   end if;
end process;

The only safe signal to use is inputFF2. So, if you want to delay that further (for example to detect an edge on it) then you'll need more flip-flops.

(VHDL) Write a double flip flop to resolve meta stability associated with asynchronous input data

1 Answers