VHDL, D-type asynchronous flip flop

Question

I just started learning vhdl code and i wrote this code for a D type asynch flip flop. How should i modify my code so that it has a second D-type, with the input to the second being fed from the output of the first?.

library ieee;
use ieee.std_logic_1164.all;

entity FLIPFLOP is
port ( 
  clk : in  std_logic ;
  clr : in  std_logic ;
  D   : in  std_logic ;
  Q   : out  std_logic
  );
end FLIPFLOP;

architecture behav of FLIPFLOP is
begin
process (clk,clr,D)
begin
if clr = '1' then
Q<= '0';
elsif rising_edge (clk) then
Q<= D;
end if;
end process;
end behav;

D isn't needed in the process sensitivity list. See VHDL D-type asynch flip flop. It's called a shift register. See Structural design of Shift Register in VHDL and Design a shift register in VHDL for example. — user1155120
process (clk, clr) variable reg: std_logic_vector(1 downto 0);begin if clk = '1' then reg := "00"; elsif rising_edge(clk) then reg := D & reg(1); end if; Q <= reg(0); end process; And if that's not what you wanted it demonstrates your question is unclear, it meets all your criteria. The two flip flops are reg(1) and reg(0). Variable reg could also be a signal, requiring the Q assignment be in another process (as in a concurrent signal assignment which is elaborated as a process statement). — user1155120

neodelphi neodelphi · Accepted Answer · 2017-10-17T20:21:45

I think you need to write a top level VHDL file which uses you DFF architecture:

entity top is
port (
  clk: in std_logic;
  clr: in std_logic;
  some_input_signal: in std_logic;
  some_output_signal: out std_logic
);
end top;

architecture rtl of top is
  signal x: std_logic;
begin
  e1: entity work.FLIPFLOP
  port map (
    clk => clk,
    clr => clr,
    D => some_input_signal,
    Q => x );

  e2: entity work.FLIPFLOP
  port map (
    clk => clk,
    clr => clr,
    D => x,
    Q => some_output_signal );
end;

x is the signal which is outputed by the first DFF and inputed to the second DFF.

VHDL, D-type asynchronous flip flop

1 Answers