My VHDL flag needs to terminate

Question

I have VHDL code that should do the following: When KEY(0)(RESET) is pressed, the next rising clock starts the process (50MHz). It sets status_flag and a new process looks at status_flag and every 1000000(+ const)clk cycles, a value called DAC is updated. I imagine as the clk-cntr is updated, it requires a few clock cycles, hence the constant. ( i used a data logger and I can see a ~20.02ms)At the bottom of the second process, clk-cntr is reset to zero. The goal is to go through the second process after KEY(0) is pressed and wait for the next KEY press. As one can see, I have status_flag commented out because the compiler responds with "can't resolve multiple constant drivers". How do I reset status_flag or similar to have the code wait for KEY(0)? I am using real time response and not simulation.

  -- ---------------------------------------------------------------------
    -- Global signals ------------------------------------------------------
    -- ---------------------------------------------------------------------
    CLK   : in std_logic;
    RESET : in std_logic;


);

end entity test_top;

architecture rtl of test_top is

 shared variable status_flag  : std_logic;
 signal clk_cntr        : unsigned(31 downto 0);
 signal DAC             : std_logic_vector(11 downto 0);

begin

DAC_Out_Rising_Edge: process(CLK)
begin 

if rising_edge(CLK) then
    if RESET = '1' then -- KEY(0) switch
            status_flag := '1'; -- The encoder is triggered on the rising edge of the clock
    end if;
end if;

end process;

    Servo_routine: process(CLK)
    begin

    if rising_edge(CLK) then -- 
        if (status_flag = '1') then
            clk_cntr <= clk_cntr + 1;

            if clk_cntr = 4 then 
                DAC <= "000000000000"; -- initialize value
            end if;
            if clk_cntr = 1000000 then
                DAC <= "000000000010";
            end if;
            if clk_cntr = 2000000 then
                DAC <= "000000000100";
            end if;
            if clk_cntr = 3000000 then
                DAC <= "000000001000";
            end if;
            if clk_cntr = 4000000 then
                DAC <= "000000010000";
            end if;
            if clk_cntr = 5000000 then
                DAC <= "000000100000";
            end if;
            if clk_cntr = 6000000 then
                DAC <= "000001000000";
            end if;
            if clk_cntr = 7000000 then
                DAC <= "000010000000";
            end if;
            if clk_cntr = 8000000 then
                DAC <= "000100000000";
            end if;
            if clk_cntr = 9000000 then
                DAC <= "001000000000";
            end if;
            if clk_cntr = 1000000 then
                DAC <= "000100000000";
            end if;
            if clk_cntr = 1100000 then
                DAC <= "000010000000";
            end if;
            if clk_cntr = 1200000 then
                DAC <= "000001000000";
            end if;
            if clk_cntr = 1300000 then
                DAC <= "000000100000";
            end if;
            if clk_cntr = 14000000 then
                DAC <= "000000010000";
            end if;
            if clk_cntr = 15000000 then
                DAC <= "000000001000";
            end if;
            if clk_cntr = 16000000 then
                DAC <= "000000000100";
            end if;
            if clk_cntr = 17000000 then
                DAC <= "000000000010";
            end if;
            if clk_cntr = 18000000 then
                DAC <= "000000000000";
            end if;

          if clk_cntr > 18000000 then
                DAC <= "000000000000";                  -- resets flags/data
                clk_cntr <= (others => '0');            -- resets flags/data
                if RESET = '0' then
                    --status_flag := '0'; -- The encoder is reset
                end if;
            end if;

        end if;  

    end if;

    end process;

Oldfart Oldfart · Accepted Answer · 2018-07-18T08:26:43

"multiple constant drivers" errors are a recurrent question asked in SE. If you put that in the search box you get 175 answers!

They all come done to the same solution: Move all assignments into one process.

if RESET = '1' then 
    status_flag := '1'; // start 
else
    if clk_cntr > 18000000 then
        status_flag := '0'; // stop 
    end if;

end if;

My VHDL flag needs to terminate

1 Answers