Delay output signal for 3 clock cycles in VHDL

Question

If the reset signal is '0' then "EN" goes high and "clr" goes low. However, if the reset signal goes high on the rising edge of the clock then "EN" goes low and "clr" goes high. I accomplished this in my code, but i need to delay the output signal produced when reset goes high[ EN = 0/ CLR = 1] for 3 more clock cycles. I tried using a counter, but it produced the same answer.

BEGIN
    process ( Reset, Clk)
    begin
        if Reset = '0' then
                En <= '1';
                clr <= '0';
        elsif rising_edge(Clk) then
            if Reset = '1' then
                En <= '0';
                clr <= '1';
            end if;
        end if;
    end process;

END description;

Paebbels Paebbels · Accepted Answer · 2015-03-27T23:11:56

Delaying signals is done by a 3 bit shift register or in your case 3 chained D-FF.

Shift register as a oneliner:

architecture rtl of myEntity is
  signal clr_sr      : std_logic_vector(2 downto 0) := "000";
  signal en_sr       : std_logic_vector(2 downto 0) := "000";
  signal clr_delayed : std_logic;
  signal en_delayed  : std_logic;
  [...]
begin
  [...]
  process(Reset, Clk)
  begin
    if Reset = '0' then
      en  <= '1';
      clr <= '0';
    elsif rising_edge(Clk) then
      en  <= '0';
      clr <= '1';
    end if;
  end process;

  clr_sr      <= clr_sr(clr_sr'high - 1 downto 0) & clr when rising_edge(Clock);
  en_sr       <= en_sr(en_sr'high - 1 downto 0)   & en  when rising_edge(Clock);
  clr_delayed <= clr_sr(clr_sr'high);
  en_delayed  <= en_sr(en_sr'high);

  [...]
end;

Or even shorter with a function sr_left to encapsulate the shift functionality:

clr_sr <= sr_left(clr_sr, clr) when rising_edge(Clock);

Delay output signal for 3 clock cycles in VHDL

1 Answers