Creating a tachometer in VDHL

Question

I have been assigned the task of creating a tachometer using VDHL to program a device. I have been provided with the pin in which an input signal will be connected and from that need to display the frequency of ones occurring per second (the frequency). Having only programmed in VHDL a couple of times previously I am having difficulty figuring out how to implement the code:

So far I have constructed the following steps that the device needs to take

Count the logical ones in the input signal by creating a process depending on it

I did this by creating a process which is dependent on the input_singal and increments a variable when a high is present in the input_signal

counthigh:process(input_signal)  -- CountHigh process
    begin
        if (input signal = '1') then
            current_count := current_count+1;
        end if;
end process; -- End process

Stop counting after a set amount of time and update the display with the frequency of the input_signal

I am unsure how to accomplish this using VHDL. I have provided a process from previous code which I used to implement a state machine. c_clk is a clock that operates at 5MHz/1024 (the timer div constant used) meaning that the period is equal to 2.048*10^-4 seconds. So the time between every rising edge is equal to that.

What I would like to do is wait for a set amount of rising_edges (I suppose I could define another variable and wait for a multiple of it to update the display and reset the current_count variable).

statereset:process  -- StateReset process
begin
    wait until rising_edge(c_clk);  -- On each rising edge
    if (reset='0') then
        current_s <= s0;  -- Default state on reset.
    else        
        current_s <= next_s;  -- Update the current state
    end if;
end process; -- End process

From previous code I already have a entity called SevenSeg which I am able to manipulate to display the current frequency of the signal using basic mathematics.

I would just like to check that by making the counthigh process dependent on the input signal the process will 'wait' until the next std_logic_vector is available and read that instead of counting a high from the input_signal numerous times. Am I able to wait until there is a rising_edge(input_singal) in one process while making another process dependent on the clock rate?

If anyone has any ideas or feedback it would be greatly appreciated. I know I am asking an extremely broad and open-ended question but I am trying to figure out how to accomplish this task.

Cheers, NZBRU.

What is Fmax of input_signal? If it's much slower than c_clk you can synchronize it to c_clk and use your current approche. Otherwise you will need to count in 2 clock domains. This requires cross clock circuits to exchange signals like start/stop from the 1 sec timer to the frequency counter. — Paebbels
An Internet search like this is a good place to start, and you can find this paper: FPGA Implementation of a Digital Tachometer. — Morten Zilmer

Jonathan Drolet Jonathan Drolet · Accepted Answer · 2015-05-12T14:17:39

counthigh:process(input_signal)  -- CountHigh process
    begin
        if (input signal = '1') then
            current_count := current_count+1;
        end if;
end process; -- End process

I understand what you are trying to achieve, but it won't work. In simulation, it will count each time input_signal goes high or low, which is good, but this code won't synthesize.

A counter needs a clock, and a process with a clock need a rising_edge. I expect your input to be of lower frequency than your operating clock, so I suggest you use an edge detector running using your clock. I will leave it as an exercise, but here's a good reference.

To wait 1 second or whatever else, use a counter. If your clock is 5MHz, use a signal to count from 0 to 4_999_999. When the counter is 4_999_999, reset the counter, the edge detector and update your display.

BTW, since your a beginner, try to use signals instead of variables. Variables have a similar behavior to programming languages, but they are a lot of pitfalls when used in synthesis. For a beginner, I suggest to stick to signals, once you're used to them and understand a little better how VHDL works, you can go back to using variables. In my own design for synthesis, I have something like 95% signals, which is standard for FPGA designers.

Creating a tachometer in VDHL

1 Answers