how to update the output on the rising edge of the clock in structural VHDL code?

Question

I have this very simple 16-bit and gate written in structural form in VHDL: The files are uploaded here.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_16bit is
  Port (
        A   : in std_logic_vector(15 downto 0);
        B   : in std_logic_vector(15 downto 0);
        Clk : in   STD_LOGIC;
        --Rst : in   STD_LOGIC;
        C   : out std_logic_vector(15 downto 0) );
end and_16bit;

architecture Behavioral of and_16bit is
component and_1bit is
  Port (
        A   : in std_logic;
        B   : in std_logic;
        C   : out std_logic );
end component;

signal s : std_logic_vector(15 downto 0);

begin
            ands: for i in 15 downto 0 generate
            and_1bit_x: and_1bit port map (A => A(i), B => B(i), C => s(i));
            end generate;
process(Clk)
    begin
        if rising_edge(Clk) then
             C <= s;                     
        end if;
        end process;
end Behavioral;

In order to update the output in the rising edge of the clock, I have defined this "s" signal. I wonder if this is the correct way to update the output in structural VHDL codes? what should I do to scape the unknown output for the first output?

Any comments will be a great help.

That's a Register Transfer Level (RTL) construct that both simulates and synthesizes. A structural representation would devolve the C register into master-slave flip flops comprised of individual gates. There isn't a lot of call for flip flops comprised of gates (transistors, resistors, diodes,...). The source for info on synthesis eligible constructs in HDL would be a synthesis vendor's documentation or the now witthdrawn IEEE Std 1076.6-2004 (typically a subset of what a vendor will accept). — user1155120
"what should I do to scape the unknown output for the first output?". Initialize s. I.e. signal s : std_logic_vector(15 downto 0) := (others => '0');. — JHBonarius

Unknown Unknown · Accepted Answer · 2017-09-25T09:49:14

It's better to put the sequential process into a submodule and instantiate it in the top-level (and_16bit). Then your top-level will be more structural.

You can have one instance for each bit as you did for and_1bit.

For example, this module is a 1-bit register.

entity dff_1bit is
    Port (
        D   : in  std_logic;
        Clk : in  std_logic;
        Q   : out std_logic );
end dff_1bit;

architecture Behavioral of dff_1bit is
begin

process(Clk)
    begin
        if rising_edge(Clk) then
             Q <= D;                     
        end if;
end process;

end Behavioral;

Then you can instantiate it in and_16bit, inside the same generate block.

dff_1bit_x: dff_1bit port map (D => s(i), Clk => Clk, Q => C(i));

how to update the output on the rising edge of the clock in structural VHDL code?

1 Answers