T flip flop VHDL code

Question

I am learning VHDL and I ran into the following code:

Entity fft is 
  port (t, r: in bit; q: out bit);
End  entity;

Architecture fft_df of fft is
signal state: bit :='0';

Begin

state <='0' when r='1' else
         not state when t='0' and t'event else
         state;

q<=state;

End;

Well, my doubt is about what this code does and if or not this is a behavioral or dataflow description of a T flip flop with reset. And than, which is the meaning of not state when t='0' and t'event? (I suppose the T flip flop works on falling edge).

Thanks to all.

There are two processes in your code, because signal assignments are processes. The code itself looks like a quite unusual description of a register with asynchronous reset. But this is not a good coding style in my eyes. — Juergen
I meant, this is a data flow description (fft_df stands for t flip flop data flow) and works on falling edge. — michele_ub
Welcome to Stack Overflow. You're more likely to get a useful answer if you follow the guidelines here. What exactly is your question? — Matthew Taylor
I just need to understand what the code above does and if that code is a VHDL dataflow approach. @MatthewTaylor — michele_ub
So, please could you edit your question to correct your typo? — Matthew Taylor

JHBonarius JHBonarius · Accepted Answer · 2018-06-27T19:25:39

I'm missing the clock input. A T-flipflop (with asynchronous reset) would actually be described by

entity tff is 
    port (clk, reset, t: in bit; q: out bit);
end entity;

architecture rtl of tff is begin
    q <= '0' when reset = '1' else
        not q when rising_egde(clk) and t = '1';
end;

Or more commonly written as:

architecture rtl of tff is begin
    tff_proc : process(clk, reset) begin
        if reset = '1' then
            q <= '0';
        elsif rising_egde(clk) then
            if t = '1' then
                q <= not q;
            end if;
        end if;
    end process;
end;

p.s. reading an output requires compiling in VHDL-2008 mode.

T flip flop VHDL code

1 Answers