Why won't this Verilog code compile?

Question

The part that causes problems is c[1] = p[0] + g[0] & c0;. What's wrong with it?

module CLA_gen(p, g, c0, c);
input [3:0] p;
input [3:0] g;
input c0;
output reg [4:1] c;
begin
c[1] = p[0] + g[0] & c0;
end
endmodule

Answer 1

You're missing your always block and its sensitivity list.

always @(*)
  c[1] = p[0] + g[0] & c0;

In the code you posted above, you don't necessarily need the begin/end since you only have one line. But it doesn't not hurt to add it in there.

Answer 2

You most likely want to change:

begin

to:

always @* begin

Every begin/end must be part of another construct, such as always, initial, etc.

Answer 3

Remove the begin and end declare c only as an output

follow this

module CLA_gen(p, g, c0, c);
input [3:0] p;
input [3:0] g;
input c0;
output [4:1] c;
assign c[1] = p[0] + g[0] & c0;
endmodule

Answer 4

You might need to use <= instead of = .