What is the wrong with this verilog code?

Question

Can anybody help me? I don't know what is wrong with it.

module add( a ,b , sum,overFlow);
  input [31:0] a;
  input  [31:0] b;
output overFlow;

  output [31:0]sum;
  reg sum;

  always @(a or b)
  begin
    sum=a+b;


  end
  initial
  begin
    if( a[30]==0 &&  b[30]==0 &&  sum[30]==1) overFlow = 1b’1;
   else if( a[30] == 1 &&  b[30] == 1 &&  sum[30] == 0) overFlow = 1b’1;

end

endmodule

the error is :

"** Error: C:/altera/13.1/add.v(13): near "b": syntax error, unexpected IDENTIFIER, expecting ';' ** Error: C:/altera/13.1/add.v(14): near "b": syntax error, unexpected IDENTIFIER, expecting ';' ** Error: C:/altera/13.1/add.v(22): near "endmodule": syntax error, unexpected endmodule "

toolic toolic · Accepted Answer · 2015-02-26T21:16:03

Change 1b’1 to 1'b1. Refer to IEEE Std 1800-2012, section "5.7 Numbers".

Once you fix that, you'll probably have other compile errors.

Change:

output overFlow;

  output [31:0]sum;
  reg sum;

to:

  output reg overFlow;
  output reg [31:0] sum;

overFlow must be a reg because you are making a procedural assignment to it (in an initial block).

What is the wrong with this verilog code?

1 Answers