Verilog : syntax error : unexpected SYSTEM_IDENTIFIER on using $display

Question

My aim is to write a test fixture that reads hex values from an input file and displays it to the screen. I am using the below code but i am getting a syntax error at line " $display ("%d:%h",j,srcPacketIn[j]);". The exact error is :

** Error: C:\altera\13.0\test.v(32): near "$display": syntax error, unexpected SYSTEM_IDENTIFIER

Could anybody please help me out?

module test_fixtures;
parameter TestCycles = 12;
parameter ClockPeriod = 10;


reg [7:0] srcPacketIn [0:(5*TestCycles)-1];

reg clock, reset;
genvar j;


initial
    begin
        $readmemh("input.h",srcPacketIn);
    end
initial
    begin
        reset = 0;
        clock = 1;
    end

always #ClockPeriod clock = ~clock;



        for (j=0; j < 59; j=j+1)
          begin
          $display ("%d:%h",j,srcPacketIn[j]);
        end
endmodule

Strangely,when i use always #<time> before $display it gets compiled — user2349990
For loops need to be inside a procedural block (always/initial/etc). Did you just not copy that part? — Tim

Victor Lyuboslavsky Victor Lyuboslavsky · Accepted Answer · 2013-08-01T21:35:27

The code works in Icarus Verilog 0.9.6 with the changes below.
Compile/sim results here: EDA Playground

module test_fixtures;
parameter TestCycles = 12;
parameter ClockPeriod = 10;


reg [7:0] srcPacketIn [0:(5*TestCycles)-1];

reg clock, reset;
integer j; // <-- CHANGED


initial
    begin
        $readmemh("input.h",srcPacketIn);
    end
initial
    begin
        reset = 0;
        clock = 1;
    end

always #ClockPeriod clock = ~clock;

initial begin // <-- ADDED
        for (j=0; j < 59; j=j+1)
          begin
          $display ("%d:%h",j,srcPacketIn[j]);
        end
      end // <-- ADDED
endmodule

Verilog : syntax error : unexpected SYSTEM_IDENTIFIER on using $display

1 Answers