Syntax error, unexpected '[', verilog

Question

I receive "syntax error, unexpected '['" in the line marked as // 2 in the following code

  module reg_file
  #(
    parameter DATA_WIDTH = 8,
          ADDR_WIDTH = 2
  )
  (
    input wire clk,
    input wire wr_en,
    input wire [ADDR_WIDTH-1:0] w_addr, r_addr,
    input wire [(DATA_WIDTH*2)-1:0] w_data,
    output wire [DATA_WIDTH-1:0] r_data
  );

  reg [DATA_WIDTH-1:0] array_reg [2 ** ADDR_WIDTH - 1:0];

  always @ (posedge clk)
    if (wr_en)
      array_reg[w_addr] <= w_data[15:8];    // 1
      array_reg[w_addr + 1] <= w_data[7:0]; // 2
  assign r_data = array_reg[r_addr];

endmodule

I want to write a 16 bit word into 8 bit register file. When I comment one of the lines marked as // 1 or // 2 - the compilation is ok. What rule have I violated? Thanks

A.Dhir A.Dhir · Accepted Answer · 2016-02-26T10:55:36

From code, it looks like you have missed out on scoping rules of the language. You have missed out to define the scope of always block in your code by missing out "begin" and "end". Moreover, you also need to define "begin" and "end" for if block as well. So your code should look like as below

module reg_file
  #(
    parameter DATA_WIDTH = 8,
          ADDR_WIDTH = 2
  )
  (
    input wire clk,
    input wire wr_en,
    input wire [ADDR_WIDTH-1:0] w_addr, r_addr,
    input wire [(DATA_WIDTH*2)-1:0] w_data,
    output wire [DATA_WIDTH-1:0] r_data
  );

  reg [DATA_WIDTH-1:0] array_reg [2 ** ADDR_WIDTH - 1:0];

  always @ (posedge clk) begin
    if (wr_en) begin
      array_reg[w_addr] <= w_data[15:8];    // 1
      array_reg[w_addr + 1] <= w_data[7:0]; // 2
    end
  end
  assign r_data = array_reg[r_addr];

endmodule

Syntax error, unexpected '[', verilog

1 Answers