Verilog output gives 'x'

Question

This is a module for a 8 bit shift register using two 4 bit shift registers. 4 bit register modules works fine. (Just testing this for right shift for the moment)

module shift_reg_8 (Out,In,shift_left,shift_right,s0,s1,enable,clock);

    output [7:0] Out;
    wire [3:0]Least_Out,Most_Out;                

    input  [7:0] In;                
    wire [3:0]Least_In,Most_In;
    reg temp;

    initial
    temp  = In[4];

    assign {Most_In,Least_In} = In;
    input shift_left,shift_right,enable,s0,s1,clock;        

    shift_reg least_sig_reg(Least_Out,Least_In,shift_left,shift_right,s0,s1,enable,clock);                
    shift_reg most_sig_reg(Most_Out,Most_In,shift_left,shift_right,s0,s1,enable,clock);         

    assign Out = {Most_Out,Least_Out};
    assign Out[3] = temp;

endmodule

Here's the test bench.

module stimulus;


reg [7:0]INPUT;
reg ENABLE,CLOCK,S0,S1,SL,SR;   

wire [7:0] OUTPUT;  

shift_reg_8 my8shiftreg(OUTPUT,INPUT,SL,SR,S0,S1,ENABLE,CLOCK);       // SL = Shift_Left, SR = Shift_Right, SO,S1 = Controls 

initial
begin

    CLOCK = 1'b0;

    INPUT = 8'b01101110; ENABLE = 1;S0 = 0;S1 = 1;SL = 0;SR = 1;
    #14 $display("Test 1 (Right Shift): INPUT = %b, S1 = %b, S0 = %b, SR = %b, OUTPUT = %b\n",INPUT,S1,S0,SR,OUTPUT);

end

always
#5 CLOCK = ~CLOCK;

    initial
#100 $stop;

endmodule

This gives an output like this when simulated.

Test 1 (Right Shift): INPUT = 01101110, S1 = 1, S0 = 0, SR = 1, OUTPUT = 1011x111

what might be the problem?

Here's the shift_reg code...

module shift_reg(Out,In,shift_left,shift_right,s0,s1,enable,clock);

    output [3:0] Out;
    input  [3:0] In;
    input shift_left,shift_right,enable,s0,s1,clock;

    reg [3:0] out_reg;

always @(posedge clock & enable)


begin

if ((s0 == 1'b0) && (s1 == 1'b0))                  // Holding 
    begin                 

    end

else if ((s0 == 1'b1) && (s1 == 1'b0))             // Left Shift
    begin

    out_reg[0] <= shift_left;
    out_reg[1] <= In[0];
    out_reg[2] <= In[1];
    out_reg[3] <= In[2];

    end

else if ((s0 == 1'b0) && (s1 == 1'b1))             // Right Shift
        begin

        out_reg[0] <= In[1];
        out_reg[1] <= In[2];
        out_reg[2] <= In[3];
        out_reg[3] <= shift_right;                        

        end

else if ((s0 == 1'b1) && (s1 == 1'b1))         // Loading 
        begin 

        out_reg <= In;          

        end 

end

assign Out = out_reg;

endmodule

Rich Maes Rich Maes · Accepted Answer · 2016-09-02T12:22:25

You are assigning out[3] twice.

assign Out = {Most_Out,Least_Out};  // Assigns all 8 bits
assign Out[3] = temp;  //  Assigns bit 3 again.

The multiple drivers is causing an unknown state.

Verilog output gives 'x'

1 Answers