VHDL program for JK Flip Flop using Case Statement

Question

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock,j,r)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
 case (jk) is
   when "00" => temp<= temp;
   when "01" => temp <= '0';
   when "10" => temp <= '1';
   when "11" => not temp;
   when others => temp <= 'X'
end case;
end process;
q <= temp;
qbar <= not temp;

end behavioral;

When I compiled this program using ghdl it is showing error 'when' is expected instead of 'not'. Please help me to find the problem with this code.

You could benefit from taking the tour. See What topics can I ask about here? Ask a specific programming question. You have numerous syntax errors. (Google BNF VHDL). Consider picking an indentation pattern you like making it easy to notice errors. Proof read. Complete error messages can be helpful to your readers who may have the same issue in the future. (Questions and answers are search resources.) — user1155120
(And to be clear process(clock,j,r) the r in the sensitivity list is a semantic error, it's not a declared signal.) — user1155120

Andrea Bellizzi Andrea Bellizzi · Accepted Answer · 2018-09-09T13:22:23

you forgot these things:

1)when "11" => not temp; to when "11" => temp <= not temp;

2)when others => temp <= 'X' must have semicolon at the end when others => temp <='X';

3)you missed end ifat the end of the if

4)process sensitivity list contains a signal named ‘r’ which is undeclared

I’ve left out the signal j and k from the process because all the code you execute in the if statement is conditioned only by the clock, so there is no need to execute the process when j and k change their value and the clock isn’t on rising edge.

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
   case (jk) is
     when "00" => temp<= temp;
     when "01" => temp <= '0';
     when "10" => temp <= '1';
     when "11" => temp <= not temp;
     when others => temp <= 'X';
    end case;
end if;
end process;
q <= temp;
qbar <= not temp;

end behavioral;

VHDL program for JK Flip Flop using Case Statement

1 Answers