VHDL signal assigement doesnt work for no apparent reason

Question

I wrote this process in my test bench for a simple 2out/1in reg file entity, here is the relevant part of the test bench: (note - those signals are std_logic_vector(X downto 0))

input : process is
begin
    wait for 30 ns;

    input_adr1  <= "00000";
    input_adr3  <= "00000";
    input_data3 <= "00000000000000000000000000000000";
    input_en3   <= '1';
    wait for 10 ns;
    input_en3 <= '0';
    wait for 10 ns;

    input_adr1  <= "00001";
    input_adr3  <= "00001";
    input_data3 <= "00000000000000000000000000000001";
    input_en3   <= '1';
    wait for 10 ns;
    input_en3 <= '0';
    wait for 10 ns;

    input_adr1  <= "00010";
    input_adr3  <= "00010";
    input_data3 <= "00000000000000000000000000000010";
    input_en3   <= '1';
    wait for 10 ns;
    input_en3 <= '0';
    wait for 10 ns;

    wait;
end process input;

However, when I go over to ModelSim to check out the waves, the signal input_data3 never changes - even though I assign it values 0000, 0001, 0002 (hex) in the sequential code. Notice that signals input_en3, input_adr3 both behave properly. Check it:

  drivers input_data3
Drivers for /procesor_tstbnch/input_data3(31:0):
   U  : Signal /procesor_tstbnch/input_data3(31)
     0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(31)
    U  : Signal /procesor_tstbnch/input_data3(30)
     0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(30)
   U  : Signal /procesor_tstbnch/input_data3(29)
     0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(29)
    U  : Signal /procesor_tstbnch/input_data3(28)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(28)
    U  : Signal /procesor_tstbnch/input_data3(27)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(27)
    U  : Signal /procesor_tstbnch/input_data3(26)
      0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(26)
   U  : Signal /procesor_tstbnch/input_data3(25)
     0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(25)
    U  : Signal /procesor_tstbnch/input_data3(24)
      0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(24)
    U  : Signal /procesor_tstbnch/input_data3(23)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(23)
    U  : Signal /procesor_tstbnch/input_data3(22)
      0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(22)
    U  : Signal /procesor_tstbnch/input_data3(21)
     0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(21)
    U  : Signal /procesor_tstbnch/input_data3(20)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(20)
   U  : Signal /procesor_tstbnch/input_data3(19)
     0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(19)
   U  : Signal /procesor_tstbnch/input_data3(18)
     0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(18)
    U  : Signal /procesor_tstbnch/input_data3(17)
     0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(17)
   U  : Signal /procesor_tstbnch/input_data3(16)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(16)
   U  : Signal /procesor_tstbnch/input_data3(15)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(15)
    U  : Signal /procesor_tstbnch/input_data3(14)
      0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(14)
    U  : Signal /procesor_tstbnch/input_data3(13)
     0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(13)
    U  : Signal /procesor_tstbnch/input_data3(12)
      0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(12)
    U  : Signal /procesor_tstbnch/input_data3(11)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(11)
    U  : Signal /procesor_tstbnch/input_data3(10)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(10)
    U  : Signal /procesor_tstbnch/input_data3(9)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(9)
    U  : Signal /procesor_tstbnch/input_data3(8)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(8)
    U  : Signal /procesor_tstbnch/input_data3(7)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(7)
    U  : Signal /procesor_tstbnch/input_data3(6)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(6)
   U  : Signal /procesor_tstbnch/input_data3(5)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(5)
    U  : Signal /procesor_tstbnch/input_data3(4)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(4)
    U  : Signal /procesor_tstbnch/input_data3(3)
     0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(3)
    U  : Signal /procesor_tstbnch/input_data3(2)
      0 : Driver /procesor_tstbnch/input
      U  : Element /procesor_tstbnch/register_file/in_data3(2)
   U  : Signal /procesor_tstbnch/input_data3(1)
      1 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(1)
    U  : Signal /procesor_tstbnch/input_data3(0)
      0 : Driver /procesor_tstbnch/input
     U  : Element /procesor_tstbnch/register_file/in_data3(0)

What am I missing? I'm not sure I understand how come this signal assignment doesn't go through.

EDIT: I've also attempted to move all the assignments to input_data3 in another process, it still never changes.

Here are the drivers of input_data3:

Are the signals shown in the waveform the exact testbench signals you're assigning, or are they the signals inside the UUT? — scary_jeff
You may want to post your question over at electronics.stackexchange.com. — JimmyB
those are from the test bench @ Hanno, thanks, ill have the in mind next time :) — Alek988Alek
Do you have another assignment to input_data3 somewhere else that is causing a multiple conflicting drivers issue? — scary_jeff
No - only those 3 (neither of which happens). The only other time input_data3 appears in my code is in a port map — Alek988Alek

EML EML · Accepted Answer · 2015-08-06T15:37:00

Check out your driver listing. For bit 1, for example, your process (Driver /procesor_tstbnch/input) is driving a 1. However, the signal is also being driven by something called /procesor_tstbnch/register_file/in_data3(1), which is driving a U. The overall result is that the bit is undefined (U).

What is register_file/in_data3?

VHDL signal assigement doesnt work for no apparent reason

1 Answers