VHDL when else doesnt work

Question

I am new to VHDL programming an FPGA, and my module ( see full code below ) doesnt work.

This module is supposed to take care if user I/O settings, based on register available to user ( so modes can be changed via register without need of touching FPGA firmware ). There are 8 input pins and 8 output pins, and 4 operation modes: 1x8, 2x8, 4x8, 8x8. Output goes into delay/gate generator module, and then out. One more function of this module is to convert 32bit input vector, where actually only 8 pins are assigned and carry a value ( specific of the FPGA - board interaction ) into something which makes more sense.

As it is now, the else catch all (00) mode which corresponds to 1x8 mode is working, no matter what the value of clockcontrolREG is. ( i am observing the correct output on oscilloscope ), so there is nothing wrong with pin assignments. It looks like for some reason all my when clauses are ignored.

I did set an initial value of clockcontrolREG to "00000011" ( which should set the mode to 8x8 ), and i did access the register and checked the value is indeed there.

I tried 2 different syntax ways to describe the same ( line: signalforclkgen(1) ), with no effect.

It looks like i am missing something very fundamental.....but it is the 3rd day i am sitting on it with no result. Thanks for all the help in advance.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clkgencontrol is
    port(
        clockcontrolREG : in  std_logic_vector(31 downto 0);
        signalinput     : in  std_logic_vector(31 downto 0);
        signalforclkgen : out std_logic_vector(7 downto 0)

        );
end clkgencontrol;


architecture rtl of clkgencontrol is

begin


    signalforclkgen(0) <= signalinput(31);

    signalforclkgen(1) <= signalinput(15) when (clockcontrolREG(0) = '1' and clockcontrolREG(1) = '1') else
                          signalinput(31);

    signalforclkgen(2) <= signalinput(30) when (clockcontrolREG = "00000011") else
                          signalinput(15) when (clockcontrolREG = "00000010") else
                          signalinput(31);

    signalforclkgen(3) <= signalinput(14) when (clockcontrolREG = "00000011") else
                          signalinput(15) when (clockcontrolREG = "00000010") else
                          signalinput(31);

    signalforclkgen(4) <= signalinput(19) when (clockcontrolREG = "00000011") else
                          signalinput(30) when (clockcontrolREG = "00000010") else
                          signalinput(15) when (clockcontrolREG = "00000001") else
                          signalinput(31);

    signalforclkgen(5) <= signalinput(3) when (clockcontrolREG = "00000011") else
                          signalinput(30)when (clockcontrolREG = "00000010") else
                          signalinput(15)when (clockcontrolREG = "00000001") else
                          signalinput(31);


    signalforclkgen(6) <= signalinput(18) when (clockcontrolREG = "00000011") else
                          signalinput(14) when (clockcontrolREG = "00000010") else
                          signalinput(15) when (clockcontrolREG = "00000001") else
                          signalinput(31);

    signalforclkgen(7) <= signalinput(2) when (clockcontrolREG = "00000011") else
                          signalinput(14) when (clockcontrolREG = "00000010") else
                          signalinput(15) when (clockcontrolREG = "00000001") else
                          signalinput(31);
end rtl;

I did confirm all WHEN clauses are ignored, by modifying the signalforclkgen(7) assignment, by making the catch all else a 0, instead of valid signal ( and ading an option for reg value of "00000000" ). and indeed there is a 0 on output. — David Hons
Quartus II v 11.0 Web, FPGA is Cyclone, if thats what you are asking about. — David Hons

Charles Steinkuehler Charles Steinkuehler · Accepted Answer · 2012-07-02T11:32:04

Are you perhaps intending to use hex constants in your comparisons? You should be getting warnings in your compile about mismatched lengths, and if you're expecting a hex value of 0x00000010 in clockcontrolREG (b00000000_00000000_00000000_00010000), that won't match the binary value you're comparing to: bxxxxxxxx_xxxxxxxx_xxxxxxxx_00000010

Try using 32-bit hex constants for your clockcontrolREG comparisons and see if that helps:

signalforclkgen(2)  <= signalinput(30) when ( clockcontrolREG = x"00000011" ) else 
                  signalinput(15) when ( clockcontrolREG = x"00000010" ) else 
                  signalinput(31);

VHDL when else doesnt work

1 Answers