Is always block needed for a generate-instantiated module to propagate the sensitivity list?

Question

I am getting confuse when coding Verilog which involves the mixture of always block, generate block and instantiation. Appreciate if somebody could help me on this.

block_A is a module which will reset x when rst signal is asserted. I tested block_A and see that x are being reset to 0 when rst signal is asserted. This is fairy straightforward.

module block_A #(parameter N=4) ( 
    input clk, rst, 
    input signed [N-1:0] w [3:0];
    output logic signed [N+2:0] x [3:0]
);

genvar i;
generate
    for (i=0; i<=3; i=i+1) begin
        always_ff @ (posedge clk, posedge rst) begin
            if (rst)    x[i] <= 0;
            else        x[i] <= x_[i];
        end
    end
endgenerate

However, when I try to instantiate multiple block_A into the top module using generate block, I observe a very strange scenario. x[6] and x[7] are not being reset to 0. Am I doing it in the wrong way? Should I create another always_ff block and put this generate block inside it? Meaning, we need to propagate the sensitivity list? It doesn't look sensible to put the generate block under the existing always_ff block as it is generated in loop fashion.

module top #(parameter N=4) (
    input clk, rst, 
    input signed [N-1:0] w [15:0],
    output logic signed [N+5:0] y [15:0]
};

logic signed [N+2:0] x [15:0];

genvar i;
generate
    for (i=0; i<=15; i=i+1) begin: pipeline_y
        always_ff @ (posedge clk, posedge rst) begin
            if (rst)    y[i] <= 0;
            else        y[i] <= y_[i];
        end
    end
endgenerate

genvar j;
generate
    for (j=0; j<=15; j=j+4) begin: my_block
        block_A #(.N(N)) my_block_A(.w(w[j+3:j]),.x(x[j+3:j]),.rst(rst),.clk(clk));
    end
endgenerate

There is not much wrong with your code. the issue is resulting from some other parts of the model. It is difficult to drive any conclusion from your examples and missing wave forms. What you said looked like a result of some race or a glitch in clk. Also 'x' itself can glitch due to a race between clk an rst and cause issues outside the code snipped you provided. — Serge
Yeah probably I should attach the full code but it's very complex and involves a lot of submodule that's why I decided to provide snippet instead. Anyway, I manage to root-caused the issue to be related to unpacked array. Instead of writing input signed [N-1:0] w [15:0], the correct way should be [15:0][N-1:0] w. This will resolve 'x' issue. Thanks btw — qwertyuiop

Oldfart Oldfart · Accepted Answer · 2018-04-21T12:37:03

First of all: your examples codes are incorrect. Both have syntax errors in them. Also it helps if you provide test bench so we can check your code without having to write one ourselves.

I can imagine that when to use 'generate' may be confusing.

The best I can come up with is that you use generate when you want to repeatedly 'place' hardware. That could be instance a module (as you do at the end of your code) or place the same logic like an assign:

wire [7:0] a,b,c [0:3];
generate
   for (i=0; i<4; i=i+1)
      assign a[i] = b[i] ^ c[i];

the example above shows that generate does not need to have an always with it.

I have taken you code and simulated it but I had to make my own test-bench. I do NOT see any X-es in my result, but the I had to heavily modify your code to work around the syntax errors thus I had to guess in several places what it should be.

Your coding style is rather unusual. The code in block_A is normally written:

always_ff @ (posedge clk, posedge rst)
begin : a_block
integer i,j;
    if (rst)
       for (i=0; i<4; i=i+1)
          x[i] <= 0;
    else
       for (j=0; j<4; j=j+1)
          x[j] <= x_[j]; // syntax error,there is no x_!
end

Which removes the need for the generate.
The use of separate index variables for the for-loops is just good coding practice.

Is always block needed for a generate-instantiated module to propagate the sensitivity list?

2 Answers