Systemverilog interface - nested interface vs modport

Question

Can I use a nested interface in place of a modport?

The purpose of this is large-scale interconnect of many different modules while taking advantage of interfaces to simplify connectivity. I prefer not to use generic interfaces ever - they are hard to follow in source code.

If I have a generic module that is used by many modules (eg, reset_synchronizer), then I could define a modport in each interface to define the signals for that module, eg:

interface xyz(input clk, input arst);
    logic srst;
    modport reset_synchronizer_mp (input clk, input arst, output srst);
endinterface

I can define this in each interface where I have the need to synchronize the reset. But when I need to change the reset_synchronizer module, perhaps to pass in an enable, I'd need to update the interface ports (add enable signal), and update each modport in all interfaces that create a modport for the reset_synchronizer.

interface xyz(input clk, input enable, input arst);
    logic srst;
    modport reset_synchronizer_mp (input clk, input enable, input arst, output srst);
endinterface

If instead of modport, I used a nested interface (reset_synchronizer_intf), couldn't I just do this inside the main interfaces:

interface xyz(input clk, input arst);
    logic srst;
    reset_synchronizer_intf reset_synchronizer_mp (clk, arst, srst);
endinterface

And to simplify this (assuming the signal names match):

interface xyz(input clk, input arst);
    logic srst
    reset_synchronizer_intf reset_synchronizer_mp (.*);
endinterface

And to add enable, I'd just be updating the main reset_synchronizer.sv (where the module and interface are defined) and update all interfaces but only at the port list or in the signal declaration:

interface xyz(input clk, input enable, input arst);
    reset_synchronizer_intf reset_synchronizer_mp (.*);
endinterface

This becomes even more attractive when the signals I'm looking for exist in the main interface, but I now want to bring them into some generic module. Eg, a power-gating module that normally only got srst, but now I want to pass in rst as well. I could change this at the interface level of the power-gating module instead of inside each interface.

dave_59 dave_59 · Accepted Answer · 2018-04-11T17:30:45

Although this works for defining structured bundles of signals, you lose the ability to specify directions with modports as they cannot be composed hierarchically. This also means you need to know the nesting when connecting to interface xyz.

module top;
xyx xyz_if(.*)

mymodule inst(xyx_if);

endmodule

module mymodule (xyz xyz_p);

...

   xyz.reset_synchronizer_mp.enable = 1;


endmodule

This most likely will not be synthesizable.

Systemverilog interface - nested interface vs modport

1 Answers