Is there an equivalent construct to this for SystemVerilog interfaces?
What I'd like to do is a bind of an interface inside some DUT block and then pass it using the UVM config DB as a virtual interface:
bind some_block some_interface(...);
interface some_interface(...);
initial
`uvm_config_db #(virtual some_interface)::set(null, "some.path", "vif", this);
endinterface
The workaround I have in place is to define a wrapper module that instantiates the interface and then does the config DB set:
module some_interface_wrapper(...);
some_interface some_if(...);
initial
`uvm_config_db #(virtual some_interface)::set(null, "some.path", "vif", some_if);
endmodule
What I don't like with this approach is that I have to define the whitebox signals twice, once in the interface and once in the wrapper module.
Is there a cleaner way to do it?
set(...)defined as a parameter that the module takes, which is assigned when it gets bound. This means any testbench can bind this module and pass it to the appropriate UVM component. - Tudor Timi