SystemVerilog replace connection with UVC using bind

Question

I have two modules connected together via an AXI interface, with module A being the master and module B being the slave, as depicted below:

  _________________________________________ 
 | top.v                                   |
 |  __________                 __________  |
 | |          |               |          | |
 | |          |<------------->|          | |
 | | module A |      AXI      | module B | |
 | |          |<------------->|          | |
 | |__________|               |__________| |
 |_________________________________________|

I want to "replace" this connection with an AXI UVC so my UVC can receive the AXI request from module A, modify it, and send the modified request to module B. I also want to inject requests to module B from my UVC, so module A wouldn't know about them, so it would look like this:

  _________________________________________ 
 | top.v                                   |
 |  __________                 __________  |
 | |          |      ___      |          | |
 | |          |<--->|   |<--->|          | |
 | | module A | AXI |UVC| AXI | module B | |
 | |          |<--->|___|<--->|          | |
 | |__________|               |__________| |
 |_________________________________________|

The caveat is that I'm not able to modify the RTL files that instantiate modules A, B, and the interface (anything in top.v). So I'd like to use bind to bind the UVC to the AXI interface, but I'm not sure if this can work as expected. My concern is that since modules A and B are still connected, they will still toggle each other's ports, e.g. if module A toggles AWVALID, it will still toggle module B's input AWVALID. Is it possible that the bind can "override" these signals?

The bind statement places an instance of the module/interface into a desired place. It cannot patch connections. So, you cannot do it with just a bind.To override signals you can use verilog 'force/release'. — Serge
If the ports are wires then force/release are not going to work. You may want to work with your designers to make them of type 'reg'. You can refer to this paper: verilab.com/files/verification_prowess_with_uvm_harness.pdf for how to use force/release in this context. — Arun D'souza

dave_59 dave_59 · Accepted Answer · 2019-11-16T22:59:53

bind cannot break a connection, it can only add to it. But there is no reason you can't modify or override the existing RTL unless it's encrypted.

SystemVerilog replace connection with UVC using bind

1 Answers