VHDL block and guarded input - what does this code do?

2
votes

I have the following from a beginner's VHDL tutorial:

   rising_edge: block(clk’event and clk = ‘1’)
    begin
        result <= guarded input or force after 10ns;
    end block rising_edge

The explanatory text is

"Essentially I have a block called rising_edge, and it's a block with a guard condition which does the following, it checks that we have an event on the clock, and that the clock is equal to one, so we're effectively looking for the so called rising_edge. We're looking for the event where the clock goes from 0 to 1, and if it does, then we can conditionally assign the results, so you'll see that the result variable here says that it is a guarded input or force after 10 ns might seem a bit confusing, but consider it without the guarded keyword. All we're doing is we're assigning the result of the evaluation of input or force, and we're doing it in a guarded setup. So, in this case, the assignment of the signal result is only executed if the guard signal is actually true, and in our example it means that the assignment of the expression, which is input or force, will only happen on the rising_edge of the clock because that's on guard condition."

Now I've read this over and over and searched on the net but have come up blanks as to what this is actually doing. Can someone please gently explain its purpose?

2
vhdl
What kind of beginners tutorial is this? Guarded expressions are ... not all that common in my experience... – user_1818839
clk’event and clk = ‘1’ doesn't guarantee a '0' to '1' transition in simulaton (use rising_edge(clk) which does). clk'event is just that any event on clk in this case to a '1' from any other value. rising_edge insures a '0' to '1' transition. – user1155120
IEEE Std 1076-2008 11.2 Block statement "If a guard condition appears after the reserved word block, then a signal with the simple name GUARD of predefined type BOOLEAN is implicitly declared at the beginning of the declarative part of the block, and the guard condition defines the value of that signal at any given time (see 14.7.4). The type of the guard condition shall be type BOOLEAN. Signal GUARD may be used to control the operation of certain statements within the block (see 11.6).{ 11.6 Concurrent signal assignment statements). Where did your tutorial come from? – user1155120
"rising_edge" is the name of a commonly used function in the std_logic_1164 library. I wouldn't re-use that word for a label of some process... – JHBonarius
A link to the tutorial you are using might be of use. – scary_jeff

2 Answers

4
votes

A block is essentially a grouping of concurrent statements. In terms of practical usage, it is very similar to a process, only it has a limited scope wich allows component-style signal mapping(with port and port map). It can be used to improve readability(see this question) and really not much else. Blocks are resonably rarely used and frequently not synthesis supported(see here). To my (limited) knowledge, the use of blocks has no other advantage than readability.

Because your block statement contains a guard condition(clk'event and clk='1' is the guard condition here), it is a guarded block. Inside a guarded block, signals that are declared guarded (like in your example) will only be assigned if the guard condition evaluates to true

The entire statement that has been guarded(i.e. in your case input or force after 10ns) will only be executed when the guard condition evaluates to true, i.e. on the rising edge of clk. Thus, for all intents and purposes this block has the same behaviour as 

process(clk)
begin
    if clk'event and clk = '1' then
        result <= input or force after 10ns;
    end if;
end process;

I will say though, this is a terrible example. For one thing, as others have stated, the usage of block is very rare and they are generally only used in quite advanced designs. The usage of clk'event and clk = '1' has been discouraged since 1993(see here). It should also be mentioned again that the usage of rising_edge as a label is a terrible idea, as is the use of force for a signal name(in VHDL 2008, force is a reserved keyword that can be used to force a signal to a value).

4
votes

Working from the idea that this is supposed to be a beginners tutorial, and with the lack of any explanation as to why such an unusual style has been used, a much more conventional implementation would be:

process : (clk)
begin
  if (rising_edge(clk)) then
    result <= input or force after 10 ns;
  end if;
end process;

A couple of points to note:

  1. This assumes that input and force are either signals, or inputs to the entity.
  2. It is unusual to model signal assignment delays if your code is going to be implemented in a real hardware device.
  3. The code in your question uses after 10ns;, which is not valid; you need a space between the value and the units (as in my code).
  4. The code in your question uses rising_edge as an identifier, when this is actually already defined as a function, assuming you are including standard IEEE libraries newer than I believe VHDL93.
  5. The code in your question uses force as a signal name, when this is also a reserved language keyword since VHDL2008.

My advice to you is to find a different tutorial. The quote you posted is not clearly written, and the code you posted appears to be sending you down a strange path. All I can think is that the tutorial is in fact very, very old.