How does this VHDL code work?

Question

I would have just put a comment in the sourced post below but I don't have that privilege yet so I thought I might just ask a question so that I can get some clarification.

how to delay a signal for several cycles in vhdl

Basically I need to implement 2 clock cycle delay to this process located in the behavioral of my VHDL project (the code for which is shown below):

  process(font_address(0), font_address(1), font_address(2), font_address(3),font_address(4), font_address(5), font_address(6), font_address(7),vga_hcount(0), vga_hcount(1),vga_hcount(2),CLK)

begin




--if (CLK'event and CLK = '1') then
  -- a_store <= a_store(1 downto 0) & a;
  -- a_out <= a_store(1 downto 0);
 --end if;

if (CLK'event and CLK = '1') then
case vga_hcount(2 downto 0) is
when "000" => font_bit <= font_data(7);
when "001" => font_bit <= font_data(6);
when "010" => font_bit <= font_data(5);
when "011" => font_bit <= font_data(4);
when "100" => font_bit <= font_data(3);
when "101" => font_bit <= font_data(2);
when "110" => font_bit <= font_data(1);
when "111" => font_bit <= font_data(0);
when others => font_bit <= font_data(0);
end case;
end if;



end process;

As you can see I have made it such that it takes a single clock cycle delay before the signal assignments in the process are made as provided by the if statement wrapped around the signal assignments but I cannot seem to create a synthesize-able 2 clock pulse delay despite reading the answered question linked above

When I comment the if statement wrapped around the case and uncomment the following block of code

 if (CLK'event and CLK = '1') then
 a_store <= a_store(1 downto 0) & a;
 a_out <= a_store(1 downto 0);
 end if;

Which was taken from the link given at the beginning of this question I get the following error:

[Synth 8-690] width mismatch in assignment; target has 2 bits, source has 3 bits ["U:/Computer organisation lab/vga/vga_prac.vhd":304]

the target being referred to in this error message is the a_store vector and the source is the concatenation of a_store and a.

This is after I assigned logic 1 to a and created a_store and a_out as std_logic_vectors with 2 elements (as I want a delay of two clock cycles). I think the reason I am getting this error is because even after reading over this question for hours I still can't seem to understand how it actually is supposed to generate a 2 clock cycle delay.

I thought at first it might be that a 1 bit gets iterated through the a_store vector until the MSB is one and then this vector is applied to a_out but looking at the fact that it is in all in an if statement I cannot see how these two lines of code would even execute more than once. If this were even true I would have to have some test to make sure that a_out has a 1 in its MSB.

Usually I would have moved on but after extensive searching I couldn't find a simpler solution than this despite the fact I don't fully understand how it is supposed to work.

If somebody could clarify this or suggest a modification to my program which will generate the required delay that would be great.

Thanks in advance,

Simon.

There are many unnecessary names in the process sensitivity list. Only CLK is required. — JHBonarius
The code you claim to have copied/pasted from the other question is in fact different. — scary_jeff
Martin's answer to your linked question shows a_store <= a_store(store'high-1 downto 0) & a; which gives the right answer. In a descending range (downto) 'high gives the index value of the left bound. For an array subtype with two elements 1 downto 0 that would be a_store(0 downto 0) an array value with one element. Your problem is you didn't implement Martin's answer faithfully. You could also provide an MCVe so the declarations are visible. Also font_bit <= font_data(to_integer(unsigned(not vga_hcount(2 downto 0)))); an 8 input multiplexer. — user1155120

JHBonarius JHBonarius · Accepted Answer · 2017-04-21T11:04:11

First off, the first code is not that efficient, and could be reduced to

use ieee.numeric_std.all;
[...]

process(CLK)
begin
    if rising_edge(CLK) then
        font_bit <= font_data(7 - to_integer(unsigned(vga_hcount(2 downto 0))));
    end if;
end process;

For the second part, the error says everything. You say a_store has 2 bits (or "elements" as you call it), then you can imagine that a_store(1 downto 0) & a is two bits of a_store + 1 bit of a = 3 bits. You cannot assign 3 bits to 2 bits. How would that fit? Same problem for assigning a_out: How can 2 bits fit into 1 bit?

Thus:

if (CLK'event and CLK = '1') then
    a_store <= a_store(0) & a;
    a_out <= a_store(1);
end if;

How does this VHDL code work?

1 Answers