VHDL My timer does not work

Question

I have a 25MHz clock in my FPGA and I would like to make a timer which returns '1' when it counts for 60 seconds. But I have two problems:

I don't understand why my outpout signal "count_sortie" is undefined in Vivado when I simulate it.
To force to define my signal count_sortie, I add ":= 0" in the testbench file to simulate but "count_sortie" stays equal to '0' after the 60 seconds delay.

Here are my VHDL files:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.all;
    use IEEE.STD_LOGIC_UNSIGNED.all;


    entity count is
        Port ( clk : in  STD_LOGIC;
               count_entree : in STD_LOGIC;
               count_sortie : out STD_LOGIC
              );
    end count;

    architecture Behavioral of count is

    signal q : integer range 0 to 30000000 :=0;

    begin

        process(clk)
        begin
        if (clk'event and clk='1')
        then 

              while ((count_entree = '1') and (q < 25000000)) loop

                 if (q < 25000000) then

                      q := q + 1;
                      count_sortie <= '0';  
                 else 

                    count_sortie <= '1';

                 end if;
              end loop;
        end if;
        end process;

    end Behavioral;

And the testbench file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY tbcount IS
END tbcount;

ARCHITECTURE behavior OF tbcount IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT count
    PORT(
           clk : in  STD_LOGIC;
           count_entree : in STD_LOGIC;
           count_sortie : out STD_LOGIC
        );
    END COMPONENT;


    --Inputs

   signal clk : std_logic := '0';
   signal count_entree : std_logic;

    --Outputs

   signal count_sortie : std_logic;

    --Clock

   constant clk_period : time := 40 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: count PORT MAP (
          clk => clk,
          count_entree => count_entree,
          count_sortie => count_sortie
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


       -- Stimulus process
   stim_proc: process
   begin        

    count_entree <= '1';

      wait;
   end process;

END;

Thank you for your support.

See this very similar question and answer: stackoverflow.com/questions/29948476/… — Josh
In architecture behavioral of count, the line q := q + 1 is syntactically wrong. If q is indeed a signal, it needs a signal assignment (<=). It is is a variable, it's not defined properly in the code you submitted. — Jonathan Drolet

Jonathan Drolet Jonathan Drolet · Accepted Answer · 2015-05-14T20:32:20

In addition to my comment on your syntax being invalid, i.e. there is a confusion wether q is a signal or a variable, the following code will not do what you expect:

while ((count_entree = '1') and (q < 25000000)) loop
    if (q < 25000000) then
        q := q + 1;
        count_sortie <= '0';  
    else 
        count_sortie <= '1';
    end if;
end loop;

This loop is either an infinite loop if it's entered while count_entree = '1' and q is a signal, or resolves to the single statement count_sortie <= '0' if q is a variable.

Your loop doesn't have any wait statement. If q is a signal, it will never be updated to a new value since this happens when a process ends or encounters a wait statement, you then get an infinite loop.

If q is a variable, the loop is unrolled and only the last assignment is effective. Note that since you exit your loop if q < 25000000, the else statements are never executed.

Finally, note that this kind of structure would not be synthesizable, if it is your end goal.

VHDL My timer does not work

2 Answers