VHDL program that chooses which operation to perform

Question

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_bit.all;
use ieee.numeric_std.all;
entity multiplexer is
port (
    A,B: in std_logic_vector (7 downto 0);
    CI: in std_logic;
    CO: out std_logic;
    ANS: out std_logic_vector (7 downto 0);
    OP: in std_logic_vector(1 downto 0);
    EN: in std_logic);
end multiplexer;

architecture archi of multiplexer is 
    signal tmp: std_logic_vector (8 downto 0);
begin
    process (EN) begin
        if (EN = '1') Then
            case OP is
            when "00" =>
                tmp <= conv_std_logic_vector((conv_integer(A)+conv_integer(B)+conv_integer(CI)),9);
                ANS<= tmp(7 downto 0);
                CO <= tmp(8);
            when "01" =>
                tmp <= conv_std_logic_vector((conv_integer(A)-conv_integer(B)+conv_integer(CI)),9);
                ANS<= tmp(7 downto 0);
                CO <= tmp(8);
            when others => NULL;

            end case;
        else
            NULL;
        end if;
    end process;
end archi;

error is coming at line 19 No feasible entries for infix operator '=' also Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. Where am I going wrong? wave output

Never use std_logic_arith, std_logic_signed, and std_logic_unsigned. This packages are not in standard. You can do everything you need with numeric_std. Besides, your code will not work, because inputs are not in the sensitivity list. And actually, I would do it with clock, to avoid hazards, and to be sure, that result is in proper time. But I'm not sure if it is necessary. — Staszek
when i removed the std_logic_arith and std_logic_unsigned and added the numeric_std.all, there were lots of errors. Most of them were concentrated around the conv_integer part of the function tmp. Also after adjusting the code , as I had made an error, in declaration of EN the program compiled and ran successfully, But there were no values in ANS and CO, they were shown as UUU ,the value was only there in tmp?. Please see the wave output I uploaded. Where am I going wrong. Please help. — Purushottam Mukhopadhyay
Well... simple. Stop using everything that comes from those libraries. Including conv_integer. Find numeric_std equivalent. For example instead of conv_integer use to_integer. As for issue with UUU in tmp - ask another question with improved code, without not standard libraries, this is longer story. — Staszek

Matthew Taylor Matthew Taylor · Accepted Answer · 2017-04-26T14:37:25

Surely this:

EN: in std_logic_vector

should be this:

EN: in std_logic

Your error message is complaining that there is no "=" operator defined that can compare a std_logic_vector to a '1', which is a literal of type std_logic.

VHDL program that chooses which operation to perform

1 Answers