Connecting a STD_LOGIC to a one bit STD_LOGIC_VECTOR

4
votes

I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard.

The problem is that it created a write enable signal (wea) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch:

Line ###: Type error near encnt ; current type std_logic; expected type std_logic_vector

How can I cast encnt, which is std_logic, to a one bit std_logic_vector?

(ISE doesn't allow me to change wea from the file of memory.)

1
castingvhdlxilinx-ise
Please show the code – JHBonarius
The VHDL term is type conversion (IEEE Std 1076-2008, 9.3.6 Type conversions) where type std_logic (a scalar type) and std_logic_vector (an array type) are not compatible, prompting scary_jeff's use of element association (6.5.6.3 Port clauses, 6.5.7 Association lists). – user1155120

1 Answers

6
votes

This is a pretty common scenario with these IP blocks. You can easily associate your std_logic signal like this:

wea(0) => encnt,

Instead of associating wea as a whole, you are just associating that one element (0). As wea only has one element, this assigns the whole vector.