VHDL RAM 256x8 bit

Question

I need to write the VHDL-code for a 256x8 bit RAM. I will use bidirectional buses to manage reading and writing, but I figured I could do that using a schematic file. What I need is to create the RAM-memory as a component, but I'm struggling somewhat, since I get several code 10818 errors. Any help would be appreciated.

The RAM memory is supposed to have one data_io port (7 downto 0 std_logic_vector), one address port (7 downto 0 std_logic_vector), as well as oe, we and clk ports (all std_logic I guess?)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY MyRAM IS 
PORT(CLOCK,WE,OE:IN STD_LOGIC;
ADDR:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D_IO: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;

ARCHITECTURE RTL OF MyRAM IS
TYPE RAM_12 IS ARRAY (0 TO 255)OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL RAM_PTR:RAM_12;
BEGIN
PROCESS(CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
RAM_PTR(CONV_INTEGER(ADDR))<=D_IO;
ELSE 
D_IO<=RAM_PTR(CONV_INTEGER(ADDR));
END IF;
END PROCESS;
END RTL;

Martin Thompson Martin Thompson · Accepted Answer · 2014-03-09T20:09:24

I'm assuming you want this to be synthesisable...

You can't use bidirectional buses directly within an FPGA. There are none inside the chip. If you write your code correctly, you can use tristate signals to infer a collection of wired-and or wired-or drivers.

However, none of that helps you with a RAM. If you want to infer a RAM inside the device it has to correspond with the actual RAM blocks available. They will have separate databuses for the write data to go in and the read data to come out. Check the helpfile for the synthesis tool you are using (probably Quartus for Altera, unless you are using a different third-party tool). There will be a section on inferring RAM blocks which will show you the exact style of coding to use.

VHDL RAM 256x8 bit

1 Answers