Entity does not match component port

Question

I have a vhdl code written for a shifter made with d-flip flops and multiplexers which runs and checks with successful syntax. However, now that i'm working on the testbench i'm running into some errors.

The VHDL Code is:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41 IS
 PORT (i3, i2, i1, i0 : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 o: OUT BIT);
END MUX41;
ARCHITECTURE arch_mux41 OF MUX41 IS
BEGIN
 PROCESS(i3, i2, i1, i0, s)
 BEGIN
 CASE s IS
 WHEN "00" => o <= i0;
 WHEN "01" => o <= i1;
 WHEN "10" => o <= i2;
 WHEN "11" => o <= i3;
 WHEN OTHERS => NULL;
 END CASE;
 END PROCESS;
END arch_mux41;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF IS
 PORT(d, clk : IN BIT;
 q, qb : OUT BIT);
END DFF;
ARCHITECTURE arch_dff OF DFF IS
BEGIN
 PROCESS(clk)
 VARIABLE q_temp : BIT;
 BEGIN
 IF(clk'EVENT AND clk='1')THEN
 q_temp := d;
 END IF;
 q <= q_temp;
 qb <= NOT q_temp;
 END PROCESS;
END arch_dff; 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY UShift IS
 PORT(clk, il, ir : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 i : IN BIT_VECTOR(3 DOWNTO 0);
 q : OUT BIT_VECTOR(3 DOWNTO 0));
END UShift;

ARCHITECTURE struct OF UShift IS

COMPONENT MUX41
 PORT (i3, i2, i1, i0 : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 o: OUT BIT);
END COMPONENT;

COMPONENT DFF
 PORT(d, clk : IN BIT;
 q, qb : OUT BIT);
END COMPONENT;

FOR U1, U2, U3, U4: MUX41 USE ENTITY WORK.MUX41(arch_mux41);
FOR U5, U6, U7, U8: DFF USE ENTITY WORK.DFF(arch_dff);
 SIGNAL o: BIT_VECTOR(3 DOWNTO 0);
 SIGNAL qb: BIT_VECTOR(3 DOWNTO 0);
 SIGNAL qt:BIT_VECTOR(3 DOWNTO 0);
BEGIN
 U1:MUX41 PORT MAP(il,qt(2), i(3), qt(3), s, o(3));
 U2:MUX41 PORT MAP(qt(3), qt(1), i(2), qt(2), s, o(2));
 U3:MUX41 PORT MAP(qt(2), qt(0), i(1), qt(1), s, o(1));
 U4:MUX41 PORT MAP(qt(1), ir, i(0), qt(0), s, o(0));
 U5:DFF PORT MAP(o(3), clk, qt(3), qb(3));
 U6:DFF PORT MAP(o(2), clk, qt(2), qb(2));
 U7:DFF PORT MAP(o(1), clk, qt(1), qb(1));
 U8:DFF PORT MAP(o(0), clk, qt(0), qb(0));
 q <= qt;
END struct;

The error messages that come up only appear when checking for the syntax in the testbench. They state that the entity does not match component port for "clk", "il", "ir", "i", "s", and "q". Does anyone have any ideas on what I may have wrong? I have read some suggestions online for similar issue but none have applied actually applied to this particular code.

The testbench is:

LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY UShift_test IS
END UShift_test;

ARCHITECTURE behavior OF UShift_test IS 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT UShift
    PORT(clk : IN  std_logic; il : IN  std_logic; ir : IN  std_logic; i : IN  std_logic_vector(3 downto 0); s:IN std_logic_vector(1 downto 0); 
    q : OUT  std_logic_vector(3 downto 0));
    END COMPONENT;

   --Inputs
   signal clk : std_logic := '0';
   signal il : std_logic := '0';
   signal ir : std_logic := '0';
   signal s : std_logic_vector(1 downto 0) := (others => '0');
   signal i : std_logic_vector(3 downto 0) := (others => '0');

    --Outputs
   signal q : std_logic_vector(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 20 ns;

BEGIN 
    -- Instantiate the Unit Under Test (UUT)
   uut: UShift PORT MAP (
          clk => clk,
          il => il,
          ir => ir,
          s => s,
          i => i,
          q => q);

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin        
   ---- test clr
      ir<= '0'; 
      wait for 40ns;
   ---- test parallel loading
        ir<= '1';
        s<= "11";
        i<= "0010";
        wait for 40ns;
     ---- test shift right
        s<= "01";
        il<='1';
    wait;   
   end process;
END;

Matthew Taylor Matthew Taylor · Accepted Answer · 2017-04-06T09:07:13

Yes. Here is the entity for UShift:

ENTITY UShift IS
 PORT(clk, il, ir : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 i : IN BIT_VECTOR(3 DOWNTO 0);
 q : OUT BIT_VECTOR(3 DOWNTO 0));
END UShift;

Here is the corresponding component in UShift_test:

COMPONENT UShift
PORT(clk : IN  std_logic; il : IN  std_logic; ir : IN  std_logic; i : IN  std_logic_vector(3 downto 0); s:IN std_logic_vector(1 downto 0); 
q : OUT  std_logic_vector(3 downto 0));
END COMPONENT;`:

As you can see, they are different. Unless you use a configuration with a port map which includes type conversion functions, the component and entity should be identical. I highly recommend you don't try to fix this using a configuration, instead I recommend you change the types to match. You have used type BIT in your designs, which is unusual. Unless there is a good reason for that, I'd change type BIT to type STD_LOGIC (and the corresponding vectors, obviously).

And, why are you using component instantiation? Direct instantiation is easier and is less typing and the extra flexibility offered by component instantiation is usually not required. Here is an example that compares the two methods: https://www.edaplayground.com/x/2QrS.

Entity does not match component port

1 Answers