VHDL Counter ones errors

Question

I already done the code, and it can work, However, when I try to write the test bench, I got some troubles on that. The input x sets up as 8 bits, and x: IN BIT_VECTOR (N -1 DOWNTO 0). When I write the test bench I connot enter the bits number.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY Count_ones IS
   GENERIC (N: INTEGER := 8); -- number of bits
   PORT ( x: IN BIT_VECTOR (N -1 DOWNTO 0); y: OUT NATURAL RANGE 0 TO N);
END ENTITY ;

architecture Behavioral of Count_ones is
    TYPE count is Array (N DOWNTO 1) OF Natural;
    signal a : count;

begin

  a(0) <= 1 when (x(0) = '1')
  else
       0;
  gen: FOR i IN N-1 DOWNTO 0
  GENERATE
            a(i+1) <= (a(i)+1) when (x(i)='0')
            else
                  a(i);
END GENERATE;

y <= a(N-1);

end Behavioral;

The Test Bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY Count_ones_TB IS
END Count_ones_TB;

ARCHITECTURE behavior OF Count_ones_TB IS 


COMPONENT Count_ones
PORT(
     x : IN  std_logic_vector(7 downto 0);
     y : OUT  std_logic_vector(0 to 3)
    );
 END COMPONENT;

--Inputs
signal x : std_logic_vector(7 downto 0) := (others => '0');

--Outputs
signal y : std_logic_vector(0 to 3);


BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Count_ones PORT MAP (
      x => x,
      y => y
    );

stim_proc: process
begin       

        x <= "00010101";
        wait for 100 ns;    
        x <= "00001001";
        wait for 100 ns;
        x <= "11111111101"
        wait for 100ns;
  -- insert stimulus here 

  wait;
end process;

END;

The error is

Entity port x does not match with type std_logic_vector of component port Entity port y does not match with type std_logic_vector of component port

Please help me, I real cannot figure out the way to solve that.

You have three locations with incorrectly constructed string literals, using single quote marks instead of double quote marks. The third on of those string values is too long. x <= "00010101"; -- '00010101';, x <= "00001001"; -- 00001001'; and `x <= "11111101"; -- '11111111101' (note it's also missing a semicolon terminating the assignment statement). Also "//" is not a comment delimiter (while "--" is). — user1155120
I got this ---Entity port x does not match with type std_logic_vector of component port, and Entity port y does not match with type std_logic_vector of component port. — N.chen
When I try to sim wave, I try to change the std_logic_vector TO std_logic, but It still not works. Thanks so much., — N.chen
Your component declaration describes ports of type std_logic_vector but your entity declartion describes ports of bit_vector and natural. — Juergen

Matthew Taylor Matthew Taylor · Accepted Answer · 2016-02-08T19:20:21

The answer to your specific question is that the types of the ports in the entity, the ports in the component and the types of the signals must match. Here is a link to your code with those errors and many more corrected.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY Count_ones IS
   GENERIC (N: INTEGER := 8); -- number of bits
   PORT ( x: IN BIT_VECTOR (N -1 DOWNTO 0); y: OUT NATURAL RANGE 0 TO N);
END ENTITY ;

architecture Behavioral of Count_ones is
    TYPE count is Array (N DOWNTO 0) OF Natural;
    signal a : count;

begin

  a(0) <= 1 when (x(0) = '1')
  else
       0;
  gen: FOR i IN N-1 DOWNTO 0
  GENERATE
            a(i+1) <= (a(i)+1) when (x(i)='0')
            else
                  a(i);
END GENERATE;

y <= a(N-1);

end Behavioral;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY Count_ones_TB IS
END Count_ones_TB;

ARCHITECTURE behavior OF Count_ones_TB IS 


COMPONENT Count_ones
   GENERIC (N: INTEGER := 8); -- number of bits
   PORT ( x: IN BIT_VECTOR (N -1 DOWNTO 0); 
          y: OUT NATURAL RANGE 0 TO N); 
END COMPONENT;

--Inputs
signal x : BIT_VECTOR(7 downto 0) := (others => '0');

--Outputs
signal y : natural;


BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Count_ones PORT MAP (
      x => x,
      y => y
    );

stim_proc: process
begin       

        x <= "00010101";
        wait for 100 ns;    
        x <= "00001001";
        wait for 100 ns;
        x <= "11111101";
        wait for 100ns;
  -- insert stimulus here 

  wait;
end process;

END;

However I must point out that you are a long way from achieving your goal of trying to count the number of ones.

Because of that:

My corrections to your code are not the only correct answer. In fact, my corrections are not even a good answer. I have simply made the minimum corrections to make your code compile and run. You need to think very carefully what type all the ports and signals in your design should be.
My corrections will not make your code work, i.e. count the number of ones.

VHDL Counter ones errors

1 Answers