How to buffer a System Verilog interface

Question

Just came across this issue and after doing a little reading, it seems that this isn't allowed in System Verilog, but it seems a little obtuse and I wonder if I am missing some easy workaround.

I have an interface that was defined as if_datapath. The interface does have some modports called sink, source and monitor and I am able to use the interface on modules without issue.

However, if I define a the interface within a module as nither sink, source or monitor:

if_datapath             #(.EW(5),.DW(256),.SW(64),.QW(32))         dp_buf_0             (.clk(clk), .reset(reset));

I can use this to route my interface through hierarchy. But if instead of using it for routing, I write the following:

always @ (posedge clk)
begin 

dp_buf_0 <= dp_in;  // Where dp_in is the same kind of 
                    //interface as dp_buf_0
end

I get an error that says:

An instance name is not a legal lvalue [7.1(IEEE)].

So if I want to register my entire interface, I need to break out the individual parts? Tell me I am missing something here.

dave_59 dave_59 · Accepted Answer · 2017-03-24T00:24:41

Interfaces and modules are just containers that create hierarchical name spaces for the items inside those containers. They also give you ways of making connections the signals within those containers. Interfaces give you a few more ways of making connections, and a modport is a construct that limits access to things inside the interface.

Interfaces are not data types, and interface instances are not variables, so you cannot perform the same kinds of operations that you would on a variable.

But you can define a struct as a data type, and then create a wire or variable using that data type. Then you can perform all the same operations that you could on a wire or variable.

How to buffer a System Verilog interface

1 Answers