VHDL: "others-like" command for std_logic signals

Question

I would like to write a code in which my W_EN (std_logic) signal is set to one at need (if some conditions are met), and otherwise (if not differently specified) is zero. If W_EN would be a std_logic_vector I could do use the "others" statement in this way to do this (in the example code "W_EN" is called "one_if_one"):

signal cnt : unsigned (1 downto 0); --incremented at every clk_cycle
signal one_if_one : std_logic;

process (cnt)
begin
one_if_one <= (others => '0');
if (cnt = "01") then
 one_if_one <= '1';
end if;
end process;

But since W_EN is only a single bit, "others" can't be used with it. So I want to ask you if there is some way for implementing the command "set to zero if not differently specified in the process".

PS: I know I could simply write the else branch of the if, but I don't want to do this, since it would be more problematic with my real code.

PPS: the only solution I've found for the moment is to replace the line:

one_if_one <= (others => '0');

with

 one_if_one <= 'L';

but this would have a different meaning since the zero imposed by "others" is a strong one.

Thank you in advance for your help.

one_if_one <= '0'; ... within a process, "last assignment wins" so you aren't creating multiple drivers on the same signal. — user_1818839
Why don't you just post your real code if you have a problem with that, instead of some hypothetical code where the problem isn't apparent? — mkrieger1
There's one driver in a process as Brian indicates, and each driver has a single transaction for each projected output waveform active at a particular simulation time (IEEE Std 1076-2008 10.5 Signal assignment statement, 10.5.2.2 Executing a simple assignment statement). Previous to your if statement assign '0' instead of an aggregate value. When the condition in your if statement is true, it's enclosed assignment supplants the previous assignment with the value '1'. Differently specified in the if statement not "... differently specified in the process". — user1155120

scary_jeff scary_jeff · Accepted Answer · 2017-01-09T09:04:29

You don't need to do anything special here. If a signal is assigned multiple times within a particular process, the last assignment is the value that actually gets assigned.

process (cnt)
begin
  one_if_one <= '0';
  if (cnt = "01") then
    one_if_one <= '1';
  end if;
end process;

Is equivalent to

process (cnt)
begin
  if (cnt = "01") then
    one_if_one <= '1';
  else
    one_if_one <= '0';
  end if;
end process;

The others syntax that you have attempted to use is exclusively for assigning array types, so it has no meaning in relation to an object of type std_logic.

VHDL: "others-like" command for std_logic signals

1 Answers