VHDL Initialize std_logic

Question

I'm writing a sequential counter which is comprised of a series of single-counter components which use D-flip-flop components. Within the single-counter, I need to start with an initial value of '0' for q, but I am having problems initializing this.

q is a STD_LOGIC signal, and I have attempted to initialize it as follows:

signal q : STD_LOGIC := '0';

However, when I run the program using ModelSim it shows a value of U as though it is unassigned. If I force freeze a signal of '0' to q when I run it in ModelSim, then it works.

Is the only way to accomplish this to check the value at the beginning of the behavioral description and set it to '0' if it is unassigned?

If I use BIT instead of STD_LOGIC, everything works perfectly.

I would post my code, but I don't want to risk academic integrity violations as this is for a school project.

Does anything else drive Q? Note that if the initial value is 0 and there is a driver driving 'U', the two values resolve to 'U'. (And if you didn't understand that, read up about resolution functions). — user_1818839
Well, I port map an output q from a D-flip-flop component to the q specified in the question. Is this what you mean? — Ryan McClure
Yes, that's your problem. You need to clear the 'U' from the flip-flop, either by resetting it, or clocking in '0' or '1'. — user_1818839

Gipsy Danger Gipsy Danger · Accepted Answer · 2015-06-23T11:41:41

The reason this works for BIT and not STD_LOGIC is because BIT has two values '1' and '0' (no value to represent uninitialized) and STD_LOGIC has 9 values one of which is 'U' which is the value that is used to say "this value hasn't been set yet".

As it's been mentioned in the comments you can solve this by assigning a value on reset - which is fairly standard practice - or clocking in a value to initialize the output (q).

If you were wondering why the initialization in your signal declaration doesn't work it's because not all synthesis tools will acknowledge this kind of initialization and ModelSim is one of those tools. When you come to put this on an FPGA, Quartus does acknowledge this kind of initialization but Lattice Diamond or Xilinx ISE might not but as most devices are provided with a POR (Power On Reset) if you include a reset condition, q will always be initialized so it's good practice to do so.

VHDL Initialize std_logic

1 Answers