Making a full adder in Verilog

Question

I'm trying to make an adder in Verilog and so far I haven't managed to do so and I was wondering if anyone could help. Here's my code:

module fulladder.v(
input a,
input b,
input c,
output sum,
output carry
);
wire (w1, w2, w3, w4);
xor(sum, a, w2);
xor(w2, b, c);
and (w3, b, c);
and (w4, b, c);
and (w5, c, a);
or (carry, w3, w4, w5);
endmodule

When I run it with fulladder.v after the module I get a syntax error but when I use fulladder (without .v) I get lots of errors:

***** START RUN *****
ERROR:HDLCompiler:806 - "fulladder.v" Line 8: Syntax error near "w1".
ERROR:HDLCompiler:1059 - "fulladder.v" Line 8: w1 is an unknown type
WARNING:HDLCompiler:329 - "fulladder.v" Line 10: Target <w2> of concurrent assignment or output port connection should be a net type.
WARNING:HDLCompiler:329 - "fulladder.v" Line 11: Target <w3> of concurrent assignment or output port connection should be a net type.
WARNING:HDLCompiler:329 - "fulladder.v" Line 12: Target <w4> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:598 - "fulladder.v" Line 1: Module <fulladder> ignored due to previous errors.
***** OUTPUT *****
***** RESULT *****
FAIL

Does anyone know what's wrong? I'd appreciate any help very much!

Thanks

Answer 1

Proper syntax is

wire w1, w2, w3, w4;

Also, you never use w1, and you use w5 but don't declare it.

Answer 2

Creating a Full Adder in Verilog is not a tough task. Definitely you must remove fulladder.v. Try the following code.

module fulladder(A,B,Cin,Sum,Cout);   
input A,B,Cin;
output Sum,Cout;
wire andout1, andout2, xorout;
xor(xorout,A,B);
xor(Sum,xorout,Cin);
and(andout1,Cin,xorout);
and(andout2,A,B);
or(Cout,andout1,andout2);
endmodule

for more details and if you want to know how to write a testbench for the full adder. follow the link below. There are several blog posts regarding the Verilog coding there.

Design a Full Adder with Verilog

Answer 3

module FA(
A,
B,
CarryIn,
Sum,
CarryOut);
input A;
input B;
input CarryIn;
output Sum;
output CarryOut;

wire w_WRITE_1;
wire w_WRITE_2;
wire w_WRITE_3;

assign w_WRITE_1=A ^ B;
assign w_WRITE_2=w_WRITE_1 & CarryIn;
assign w_WRITE_3=A & B;
assign Sum=w_WRITE_1 ^ CarryIn;
assign CarryOut=w_WRITE_2 | w_WRITE_3;

endmodule