Error: Unexpected module instantiations outside module boundaries

Question

I am trying to create a 32-bit counter that breaks the 32 inputs into 4 groups of 8 then feeds those 4 groups into a mux. This is what I have:

modules Bit32 ( clk, reset, load, D, Q);
input clk, reset, load, D, Q;
input [7:0] D;
input [15:8] D;
input [23:16] D;
input [31:24] D;
output [7:0] Q;
output [15:8] Q;
output [23:16] Q;
output [31:24] Q;
reg [7:0] Q;
reg [15:8] Q;
reg [23:16] Q;
reg [31:24] Q;
always @(posedge clk)
    if(reset) Q <=32'b0; else 
    if (load) Q <=D;
    else Q <=Q + 32'b1
endmodule

I receive these errors:

ERROR:HDLCompiler:944 - "C:/Users/Skyla/Documents/csulb/Fall17/201/assign5/Bit32.v" Line 1: Unexpected module instantiations outside module boundaries.

WARNING:HDLCompiler:1591 - "C:/Users/Skyla/Documents/csulb/Fall17/201/assign5/Bit32.v" Line 1: Root scope declaration is not allowed in verilog 95/2K mode

ERROR:HDLCompiler:806 - "C:/Users/Skyla/Documents/csulb/Fall17/201/assign5/Bit32.v" Line 2: Syntax error near "input".

My mux:

module CounterMux(select, D, Q);
input[1:0] select;
input[3:0] D:
output Q;

wire Q;
wire [1:0] select;
wire [3:0] D;

assign Q=D[select];

endmodule

In Bit32 you declared D and Q 5 times ( 1 as single bit, 4 as 8-bits). In CounterMux there is an obvious typo. I suggest you learn and implent an ANSI header style. It is fewer lines of code, easier to read, and less error prone. The Non-ANSI style if for backward comparability support. — Greg
@Greg Im using verilog hdl, im not sure what is ANSI? I'm just a beginner — Skyla Kaytlin
stackoverflow.com/search?q=%5Bverilog%5D+ANSI most answers have direct quotes and links form IEEE1364 (Verilog) and the IEEE1800 (SystemVerilog) — Greg

toolic toolic · Accepted Answer · 2020-05-04T17:47:34

The errors and warnings for the Bit32.v file are due to a typo: the keyword is module, not modules (notice the "s"). Change:

modules Bit32 ( clk, reset, load, D, Q);

to:

module Bit32 ( clk, reset, load, D, Q);

The compiler thought you were placing an instance of a module named modules . Making that change gets rid of the messages you showed.

But there are other errors in the Bit32.v file. You should not declare multiple ports with the same name. You declared D and Q 5 times each, but they must only be declared once each. For example:

module Bit32 ( clk, reset, load, D, Q);
input clk, reset, load;
input [31:0] D;
output [31:0] Q;
reg [31:0] Q;
always @(posedge clk)
    if (reset) Q <= 32'b0;
    else if (load) Q <= D;
    else Q <= Q + 32'b1;
endmodule

I also got a compile error because there was a missing semicolon after else Q <=Q + 32'b1. I believe the IEEE Std requires a semicolon after each statement. Although some compilers apparently don't require it, it is best to have it for portability.

Error: Unexpected module instantiations outside module boundaries

1 Answers