verilog Syntax error(HDLCompiler:806)

Question

I am new to Verilog and I'm keep getting these compile errors. I've googled the error, but i didn't get an answer. Here is my code and the errors.

always @(*) begin
     //seed=32'habcd123cd;//assigning seed
     if(posedge axi_clk & first[0]) begin
          load_seed=1'b1;
     end

     if(load_seed) begin
          first[1]=1'b1;
     end

     if(negedge axi_clk & first[1]) begin
          load_seed=1'b0;
          first=2'b00;
     end
 end

My errors

ERROR:HDLCompiler:806 - "K:/final project/codes/v2/input_arbiter.v" Line 252: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "K:/final project/codes/v2/input_arbiter.v" Line 258: Syntax error near "negedge".
ERROR:HDLCompiler:598 - "K:/final project/codes/v2/input_arbiter.v" Line 46: Module ignored due to previous errors.

Qiu Qiu · Accepted Answer · 2015-08-18T10:11:15

You're using posedge/negedge in a wrong way. These keywords should be used in a sensitivity list of always block, e.g.:

always @(posedge clk)

or

always @(negedge clk)

always @(*) is used to describe combinational logic, or logic gates. What you're trying to achieve is sequential logic.

You should also know (please refer to this topic) that

when you assign to a register in an edge-sensitive always block, you're defining a flip-flop. FPGAs do not have flip-flops that can trigger on both edges of a clock. That's why you need two separate always blocks, one for each edge of the clock, and then figure out a way to combine the outputs of the two blocks without creating glitches.

verilog Syntax error(HDLCompiler:806)

1 Answers