VERILOG issue with struct

Question

I have an unsolved problem with the use of struct in Verilog.

Here is my code :

//Other technic
//typedef struct{bit Over_I;}reg_type;

// Code 
module Overload(rst_n,clock,vlowp,IHigh,Over_I);

    // Port declaration
    input rst_n,clock,vlowp,IHigh;
    output Over_I;

    reg S_NOM = 0;
    reg S_OVL = 1;

    struct{
        reg Over_I;
    } reg_type;

    reg_type Reg,NextReg;

    initial
    begin 
        Over_I = Reg.Over_I;
    end

I tried with a typedef outside the module without success.

The error given by the console is :

"ERROR:HDLCompiler:806 - "C:/....../Lattice_tests/Test_Verilog/sources/overload_test.v" Line 26: Syntax error near "{".

The line 26 is the line where i defined struct.

If someone can help me, i would be grateful. Thanks. Franckois

Greg Greg · Accepted Answer · 2016-04-19T16:52:05

Verilog does not support struct data types. SystemVerilog (the successor of Verilog) does. All modern Verilog simulators are SystemVerilog simulators. You can enable SystemVerilog by changing the file extinction from .v to .sv
Most simulators have a compile option to force all Verilog files as SystemVerilog, but you will need to refer to the manual and it is not recommended. There is a lot of legacy Verilog code that used variable/net names that conflict with SystemVerilog keywords (ex bit and byte). The simulator can correctly parse the files correctly if the file extensions are used correctly.

Also initial will only assign something once. Over_I will not have the value of Reg.Over_I after time 0. Plus a wire (the default type of an output) cannot be assigned within a procedural block (eg initial and always blocks). Use an assign statement or make it an output reg and assign it in an (assuming SystemVerilog) always_comb or always_ff block, or Verilog always block.

VERILOG issue with struct

1 Answers