Verilog forcing struct to be packed

Question

I have a struct declared inside a module like this:

module myModule;

  struct {
    logic a;
    logic b;
    logic [A - 1:0] c[0:B - 1];
    logic [C - 1:0] d;
  } [D - 1:0] e [0:E - 1][0:F - 1];

endmodule

I want to use c like an unpacked array, but Verilog does not allow this. It throws an error on the line where c is defined:

Unsupported: Unpacked array in packed struct/union

Is there a way around this?

Since c is an unpacked variable, you can not used packed structures of SV. The following will work: typedef struct packed{ logic a; logic b; logic [A - 1:0] c[0:B - 1]; logic [C - -1:0] d; } mystruct; mystruct e [0:E - 1][0:F - 1]; Note that e should not have a packed dimension since it is an array of struct variables. — sharvil111

dave_59 dave_59 · Accepted Answer · 2017-05-05T04:19:37

In order to have a packed array, all element must be packed. So either make the struct packed:

struct packed {
    logic a;
    logic b;
    logic [A - 1:0] [0:B - 1] c;
    logic [C - 1:0] d;
  } [D - 1:0] e [0:E - 1][0:F - 1];

or make the e array all unpacked

  struct {
        logic a;
        logic b;
        logic [A - 1:0] [0:B - 1] c;
        logic [C - 1:0] d;
      } e [0:E - 1][0:F - 1][D - 1:0];

BTW, it is highly recommended that you use a typedef for your struct instead of having an anonymous struct type.

Verilog forcing struct to be packed

1 Answers